Abstract: In an insulated gate semiconductor device, a loss is suppressed and a short-circuit tolerance as well as a latch-up tolerance are improved. A saturation current I.sub.CE (sat) and a short-circuit tolerance tw are reduced without much influencing a collector-emitter saturation voltage V.sub.CE (sat) by setting a sheet resistance of an n-type emitter region 4 at a large value. When the sheet resistance is in the range between 40.OMEGA./.quadrature. and 150.OMEGA./.quadrature., 10 .mu.sec or more of the short-circuit tolerance, which is practically sufficient, is ensured while the collector-emitter saturation voltage V.sub.CE (sat) is suppressed to practically small 2.4 V or less. Both the collector-emitter saturation voltage V.sub.CE (sat) and the saturation current I.sub.CE (sat) are restrained small, thereby realizing an enhanced short-circuit tolerance.

Abstract: An improved insulated gate semiconductor device comprises a high-concentration p-type semiconductor region formed widely enough to protrude over n-type emitter regions without reaching an n-type epitaxial layer over a p-type base region only in first regions wherein the n-type emitter regions are wider than second regions as viewed from the top of the device. A gate threshold voltage V.sub.GE (th) has a relatively high level V.sub.GE (th-High) in the first regions, so that a low collector-emitter saturation voltage V.sub.CE (sat) and a low saturation current I.sub.CE (sat) are achieved. This provides for a high short-circuit tolerance as well as a high latch-up tolerance with low losses.

Abstract: An IGBT has an emitter bypass structure. The interval D between N emitter regions is adapted to be larger than two times of a channel length L in order to effectively decrease a channel width to effectively decrease a saturation current. A high concentration region may be provided in a P base region, which is closer to the end portion of the P base region than the emitter regions between the emitter regions, so that the channel width can be effectively decreased even without the relation of D>2L. A channel width per unit area W.sub.U may be in a range of 140 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.280 cm.sup.-1 in an IGBT of a breakdown voltage class of 500-750 V or 70 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.150 cm.sup.-1 in an IGBT of a breakdown voltage class of 1000-1500 V, so that an IGBT having a short-circuit withstandability and a latch-up withstandability suitable for an inverter can be implemented.

Abstract: An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of a top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.sup.

Abstract: An improved insulated gate semiconductor device comprises a high-concentration p-type semiconductor region formed widely enough to protrude over n-type emitter regions without reaching an n-type epitaxial layer over a p-type base region only in first regions wherein the n-type emitter regions are wider than second regions as viewed from the top of the device. A gate threshold voltage V.sub.GE (th) has a relatively high level V.sub.GE (th-High) in the first regions, so that a low collector-emitter saturation voltage V.sub.CE (sat) and a low saturation current I.sub.CE (sat) are achieved. This provides for a high short-circuit tolerance as well as a high latch-up tolerance with low losses.

Abstract: An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of an top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.

Abstract: The present invention direct to a semiconductor device and a method of manufacturing the same. According to the semiconductor device of the present invention, a first region is partially formed on a major surface of a semiconductor substrate so as to have the opposite conductivity to the first region, and an electrode is formed on the major surface. A barrier layer may be formed between the region adjacent to the first region of the semiconductor substrate and the electrode in order to reduce a current flowing in a parasitic diode. Or, an area of a connecting part between the first region and the electrode may be set to be larger than that of a connecting part between the region adjacent to the first region of the semiconductor substrate and the electrode in order to reduce a current flowing in a parasitic diode. Or, both of technique mentioned above may be combined to reduce a current flowing in a parasitic diode. Thus, it is possible to provide a semiconductor device which can be fit for high-frequency use.

Abstract: An IGBT has an emitter bypass structure. The interval D between N emitter regions is adapted to be larger than two times of a channel length L in order to effectively decrease a channel width to effectively decrease a saturation current. A high concentration region may be provided in a P base region, which is closer to the end portion of the P base region than the emitter regions between the emitter regions, so that the channel width can be effectively decreased even without the relation of D>2L. A channel width per unit area W.sub.U may be in a range of 140 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.280 cm.sup.-1 in an IGBT of a breakdown voltage class of 500-750 V or 70 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.150 cm.sup.-1 in an IGBT of a breakdown voltage class of 1000-1500 V, so that an IGBT having a short-circuit withstandability and a latch-up withstandability suitable for an inverter can be implemented.

Abstract: The present invention direct to a semiconductor device and a method of manufacturing the same. According to the semiconductor device of the present invention, a first region is partially formed on a major surface of a semiconductor substrate so as to have the opposite conductivity to the first region, and an electrode is formed on the major surface. A barrier layer may be formed between the region adjacent to the first region of the semiconductor substrate and the electrode in order to reduce a current flowing in a parasitic diode. Or, an area of a connecting part between the first region and the electrode may be set to be larger than that of a connecting part between the region adjacent to the first region of the semiconductor substrate and the electrode in order to reduce a current flowing in a parasitic diode. Or, both of technique mentioned above may be combined to reduce a current flowing in a parasitic diode. Thus, it is possible to provide a semiconductor device which can be fit for high-frequency use.

Abstract: A P-type base region, which is formed on an N-type body layer, as a relatively deep first base region and a relatively shallow second base region. An N.sup.+ -type emitter region is formed on the base region. A portion of the surface of the second base region between surfaces of the emitter region and body layer is defined as a channel. A gate oxide film, on which a gate electrode is formed, is provided on the channel. The amount and depth of introduction of an impurity in the second base region is about 2.times.10.sup.14 to 5.times.10.sup.14 cm.sup.-2 and 4 to 10 .mu.m, respectively. The thickness of the gate oxide film is about 600 to 1000 .ANG.. Thus, an IGBT is implemented, which can ensure sufficient pulse energization ability while causing no latch-up in application to a stroboscope circuit.

Abstract: An IGBT has an emitter bypass structure. The interval D between N emitter regions is adapted to be larger than two times of a channel length L in order to effectively decrease a channel width to effectively decrease a saturation current. A high concentration region may be provided in a P base region, which is closer to the end portion of the P base region than the emitter regions between the emitter regions, so that the channel width can be effectively decreased even without the relation of D>2L. A channel width per unit area W.sub.U may be in a range of 140 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.280 cm.sup.-1 in an IGBT of a breakdown voltage class of 500-750 V or 70 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.150 cm.sup.-1 in an IGBT of a breakdown voltage class of 1000-1500 V, so that an IGBT having a short-circuit withstandability and a latch-up withstandability suitable for an inverter can be implemented.

Abstract: A P-type base region, which is formed on an N-type body layer, has a relatively deep first base region and a relatively shallow second base region. An N.sup.+ -type emitter region is formed on the base region. A portion of the surface of the second base region between surfaces of the emitter region and body layer is defined as a channel. A gate oxide film, on which a gate electrode is formed, is provided on the channel. The amount and depth of introduction of an impurity in the second base region is about 2.times.10.sup.14 to 5.times.10.sup.14 cm.sup.-2 and 4 to 10 .mu.m, respectively. The thickness of the gate oxide film is about 600 to 1000 .ANG.. Thus, an IGBT is implemented, which can ensure sufficient pulse energization ability while causing no latch-up in application to a stroboscope circuit.

Abstract: A method of producing a gate turn-off thyristor includes producing a first n type impurity region, a second p type impurity region, a third n type impurity region, and a fourth p type impurity region produced in a semiconductor substrate providing a cathode electrode in contact with the first n type impurity region, providing a gate electrode in contact with the second p type impurity region, and an anode electrode which short-circuits the third and the fourth regions at the second main surface of the semiconductor substrate. Gold is diffused into the third region at a predetermined diffusion temperature thereby shortening the life time of carriers in the substrate.

Abstract: A semiconductor device includes a semiconductor element (21) having a cathode (21d) divided into a plurality of islands, each of the cathode islands (21d) being electrically connected through a cathode insert (24). The cathode insert (24) comprises a cup-shaped first conductor (241, 245) and a second conductor (242, 246) fitted into and kept in electrical contact with the first conductor (241, 245). The cup-shaped first conductor (241, 245) is disposed such that its bottom is in electrical contact with the plurality of the cathode islands (21d). The cathode side of the semiconductor element (21) is pressed against the anode side thereof for good liberation of heat.

Abstract: A polycrystalline silicon film is disposed on the face of an N type silicon substrate including a termination of a PN junction to extend slightly beyond the termination of the PN junction from the periphery of the substrate. In the most preferred embodiment, the polycrystalline silicon film terminates short of both the termination of the PN junction and the periphery of the substrate and is enclosed with silicon dioxide, the silicon dioxide being also disposed at the termination of the PN junction and on the adjacent portions of the main substrate face on its both side as well as on the periphery of the main face.

Abstract: A silicon dioxide film and a silicon nitride film are successively vapor-deposited on a main face of an N type silicon substrate processed with H.sub.2 O.sub.2 water. Those portions of both films underlaid by a P type region to be subsequently formed and their peripheral portions are selectively removed. Then a P type impurity is diffused into the central exposed portion of the main substrate face to form the P type region with a PN junction having a termination facing the silicon dioxide film. Also a silicon dioxide film is thermally formed on the peripheral exposed portion of the main face.