Patents by Inventor Hiroyasu Ishida
Hiroyasu Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951831Abstract: A tractor includes an engine, a vehicle body, a rear PTO shaft, a central PTO shaft, a permission switch, and a control unit. The engine is configured to generate power. The vehicle body includes an operator's seat. The rear PTO shaft is configured to supply power generated by the engine to a rear work machine attached to a rear part of the vehicle body. The central PTO shaft is configured to supply power generated by the engine to a central work machine attached to a central part of the vehicle body. The permission switch is operable by an operator. The control unit indicates that the permission switch is operated as one of permission conditions for rotation of the rear PTO shaft after disembarkation, and indicates that the permission switch is operated as one of permission conditions for rotation of the central PTO shaft when moving backward.Type: GrantFiled: May 5, 2023Date of Patent: April 9, 2024Assignee: YANMAR HOLDINGS CO., LTD.Inventors: Hiroyasu Ishida, Tetsuya Iida
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Publication number: 20230364991Abstract: A tractor includes an engine, a vehicle body, a rear PTO shaft, a central PTO shaft, a permission switch, and a control unit. The engine is configured to generate power. The vehicle body includes an operator's seat. The rear PTO shaft is configured to supply power generated by the engine to a rear work machine attached to a rear part of the vehicle body. The central PTO shaft is configured to supply power generated by the engine to a central work machine attached to a central part of the vehicle body. The permission switch is operable by an operator. The control unit indicates that the permission switch is operated as one of permission conditions for rotation of the rear PTO shaft after disembarkation, and indicates that the permission switch is operated as one of permission conditions for rotation of the central PTO shaft when moving backward.Type: ApplicationFiled: May 5, 2023Publication date: November 16, 2023Applicant: Yanmar Holdings Co., Ltd.Inventors: Hiroyasu ISHIDA, Tetsuya IIDA
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Patent number: 10976742Abstract: A ship handling device executing dynamic positioning control with which the fixed-point maintaining accuracy including measurement accuracy of a satellite positioning system can be assessed. In this ship handling device for maintaining a ship body at a target position using a GNSS (Global Navigation Satellite System) device, a positioning accuracy level of the GNSS device is calculated based on a radio-wave reception state of the GNSS device, a fixed-point deviation amount level is calculated based on a fixed-point deviation amount calculated based on the target position and a measured position measured by the GNSS device, and a fixed-point maintaining accuracy level indicative of an assumed range of an absolute position of the ship body relative to the target position is determined with reference to the positioning accuracy level and the fixed-point deviation amount level.Type: GrantFiled: March 10, 2017Date of Patent: April 13, 2021Assignee: YANMAR POWER TECHNOLOGY CO., LTD.Inventors: Hiroyasu Ishida, Akiyoshi Hayashi, Toshiaki Naega
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Publication number: 20190079197Abstract: A ship handling device executing dynamic positioning control with which the fixed-point maintaining accuracy including measurement accuracy of a satellite positioning system can be assessed. In this ship handling device (7) for maintaining a ship body (1) at a target position (Y) using a GNSS (Global Navigation Satellite System) device (13), a positioning accuracy level (19) of the GNSS device is calculated based on a radio-wave reception state of the GNSS device, a fixed-point deviation amount level (20) is calculated based on a fixed-point deviation amount calculated based on the target position and a measured position (X) measured by the GNSS device, and a fixed-point maintaining accuracy level (21) indicative of an assumed range of an absolute position (Z) of the ship body relative to the target position is determined with reference to the positioning accuracy level and the fixed-point deviation amount level.Type: ApplicationFiled: March 10, 2017Publication date: March 14, 2019Applicant: Yanmar Co., Ltd.Inventors: Hiroyasu ISHIDA, Akiyoshi HAYASHI, Toshiaki NAEGA
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Patent number: 9027691Abstract: A driving unit for use in an electric assist bicycle includes a rotation detection device in addition to a torque detection device such that the detection resolution of the rotation detection device is increased. The driving unit includes a housing, a crankshaft, a torque detection device, a rotating member, and a rotation detection device. The rotating member includes a connecting shaft and an output shaft. The connecting shaft is located at one of the ends of the rotating member disposed along its axis, and is coupled with the crankshaft in the housing. The output shaft is located at the other one of the ends of the rotating member disposed along its axis. The rotation detection device includes a detected portion and a detector. The detected portion is provided on the rotating member, and located around the central axis of the crankshaft in the housing.Type: GrantFiled: December 12, 2013Date of Patent: May 12, 2015Assignee: Yamaha Hatsudoki Kabushiki KaishaInventors: Hiroyasu Ishida, Noriyasu Ishikawa, Shinnosuke Moji
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Publication number: 20140166384Abstract: A driving unit for use in an electric assist bicycle includes a rotation detection device in addition to a torque detection device such that the detection resolution of the rotation detection device is increased. The driving unit includes a housing, a crankshaft, a torque detection device, a rotating member, and a rotation detection device. The rotating member includes a connecting shaft and an output shaft. The connecting shaft is located at one of the ends of the rotating member disposed along its axis, and is coupled with the crankshaft in the housing. The output shaft is located at the other one of the ends of the rotating member disposed along its axis. The rotation detection device includes a detected portion and a detector. The detected portion is provided on the rotating member, and located around the central axis of the crankshaft in the housing.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Hiroyasu ISHIDA, Noriyasu ISHIKAWA, Shinnosuke MOJI
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Patent number: 8717557Abstract: A spectrophotometer includes a xenon flash lamp, a spectroscope, and a light detector, wherein the spectrophotometer is configured to arrange a low-pressure mercury lamp on a bundle of light rays between the xenon flash lamp and the spectroscope on an as needed basis upon a performance determination of the spectrophotometer, and has a shutter mechanism that switches between shielding the bundle of light rays emitted from the low-pressure mercury lamp and allowing the bundle of light rays to pass through. A processing unit determines the performance of the spectrophotometer by detecting each of the light intensities with the light detector at the time when shielding the bundle of light rays and at the time when allowing the bundle of light rays by operating the shutter mechanism.Type: GrantFiled: February 16, 2011Date of Patent: May 6, 2014Assignee: Hitachi High-Technologies CorporationInventors: Hayato Tobe, Yoichi Sato, Hiroyasu Ishida, Takayuki Wakui
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Patent number: 8344457Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.Type: GrantFiled: February 24, 2010Date of Patent: January 1, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Yasunari Noguchi, Eio Onodera, Hiroyasu Ishida
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Publication number: 20120307240Abstract: Provided are a spectrophotometer using a xenon flash lamp and which can compare with data stored in the past, and a method for determining the performance of the spectrophotometer. In normal times, spectroscopic analysis is performed by employing a bundle of light rays emitted from the xenon flash lamp, spectrally separating the bundle of light rays into arbitrarily-defined wavelengths with a spectroscope through a concave mirror, and detecting the bundle of light rays having passed through a sample with a photodetector. When the performance is to be determined, a low-pressure mercury lamp is arranged in a path of the bundle of light rays between the xenon flash lamp and the spectroscope, a light-shield plate which constitutes a shutter mechanism is operated to shield the light and allow the light to pass through, and the intensity of the light is detected, to thereby determine the “wavelength accuracy” or the “resolution” by employing the bright-line spectrum of the low-pressure mercury lamp.Type: ApplicationFiled: February 16, 2011Publication date: December 6, 2012Inventors: Hayato Tobe, Yoichi Sato, Hiroyasu Ishida, Takayuki Wakui
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Patent number: 8253207Abstract: By integrating a diode and a resistor connected in parallel into the same chip as an IGBT and connecting a cathode of the diode to a gate of the IGBT, the value of dv/dt can be limited to a predetermined range inside the chip of the IGBT without a deterioration in turn-on characteristics. Since the chip includes a resistor having such a resistance that a dv/dt breakdown of the IGBT can be prevented, the IGBT can be prevented from being broken by an increase in dv/dt at a site (user site) to which the chip is supplied.Type: GrantFiled: December 23, 2009Date of Patent: August 28, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Shuji Yoneda, Hiroyasu Ishida, Makoto Oikawa
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Patent number: 8217486Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.Type: GrantFiled: September 23, 2008Date of Patent: July 10, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Hiroyasu Ishida, Yasuyuki Sayama
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Patent number: 8133788Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.Type: GrantFiled: September 25, 2009Date of Patent: March 13, 2012Assignee: Semiconductor Components Industries, LLCInventors: Yasuyuki Sayama, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Kazunari Kushiyama
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Patent number: 7902053Abstract: Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.Type: GrantFiled: August 27, 2008Date of Patent: March 8, 2011Assignees: Sanyo Electric Co., Ltd, Sanyo Semiconductor Co., LtdInventors: Hiroyasu Ishida, Yasuyuki Sayama
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Patent number: 7825474Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.Type: GrantFiled: September 24, 2007Date of Patent: November 2, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Yasunari Noguchi, Eio Onodera, Hiroyasu Ishida
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Patent number: 7777316Abstract: Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.Type: GrantFiled: September 26, 2008Date of Patent: August 17, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Hiroyasu Ishida, Yasuyuki Sayama, Tetsuya Okada
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Publication number: 20100163922Abstract: By integrating a diode and a resistor connected in parallel into the same chip as an IGBT and connecting a cathode of the diode to a gate of the IGBT, the value of dv/dt can be limited to a predetermined range inside the chip of the IGBT without a deterioration in turn-on characteristics. Since the chip includes a resistor having such a resistance that a dv/dt breakdown of the IGBT can be prevented, the IGBT can be prevented from being broken by an increase in dv/dt at a site (user site) to which the chip is supplied.Type: ApplicationFiled: December 23, 2009Publication date: July 1, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Shuji Yoneda, Hiroyasu Ishida, Makoto Oikawa
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Publication number: 20100148268Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.Type: ApplicationFiled: February 24, 2010Publication date: June 17, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yasunari NOGUCHI, Eio ONODERA, Hiroyasu ISHIDA
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Patent number: 7732869Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.Type: GrantFiled: September 25, 2007Date of Patent: June 8, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Yasunari Noguchi, Eio Onodera, Hiroyasu Ishida
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Patent number: 7692240Abstract: Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad electrode, are kept at a predetermined potential. Thus, a predetermined drain-source reverse breakdown voltage can be secured without providing a p+ type impurity region on the entire surface below the gate pad electrode.Type: GrantFiled: May 8, 2007Date of Patent: April 6, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroyasu Ishida, Yasunari Noguchi
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Publication number: 20100015772Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.Type: ApplicationFiled: September 25, 2009Publication date: January 21, 2010Applicant: SANYO Electric Co., Ltd.Inventors: Yasuyuki SAYAMA, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Kazunari Kushiyama