Patents by Inventor Hiroyasu Itou
Hiroyasu Itou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7691697Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.Type: GrantFiled: June 24, 2008Date of Patent: April 6, 2010Assignee: DENSO CORPORATIONInventor: Hiroyasu Itou
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Publication number: 20080311740Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.Type: ApplicationFiled: June 24, 2008Publication date: December 18, 2008Applicant: DENSO CORPORATIONInventor: Hiroyasu Itou
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Patent number: 7416932Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.Type: GrantFiled: April 19, 2007Date of Patent: August 26, 2008Assignee: DENSO CORPORATIONInventor: Hiroyasu Itou
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Publication number: 20070187841Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion- of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.Type: ApplicationFiled: April 19, 2007Publication date: August 16, 2007Applicant: DENSO CORPORATIONInventor: Hiroyasu Itou
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Patent number: 7235844Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.Type: GrantFiled: May 19, 2005Date of Patent: June 26, 2007Assignee: Denso CorporationInventor: Hiroyasu Itou
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Publication number: 20050258484Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.Type: ApplicationFiled: May 19, 2005Publication date: November 24, 2005Inventor: Hiroyasu Itou
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Patent number: 6914288Abstract: A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.Type: GrantFiled: September 12, 2003Date of Patent: July 5, 2005Assignee: Denso CorporationInventors: Hiroyasu Itou, Mitsutaka Katada, Hidetoshi Muramoto
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Patent number: 6791156Abstract: In a manufacturing process of an SOI structure semiconductor device in which an MOS capacitor is located on an SOI substrate, the capacitor insulating film of the MOS capacitor is prevented from degrading due to a bimetal effect, which is caused by a thermal treatment and characteristic to the SOI substrate. A trench is formed to surround the MOS capacitor in the SOI substrate, thick oxide films are formed on sidewalls defining the trench, and the trench is filled with polysilicon to complete a trench isolation layer. Because the thick oxide films have a coefficient of thermal expansion that is different from that of a silicon semiconductor layer of the SOI substrate, the thick oxide films are able to prevent the capacitor insulating film from degrading in film quality due to the thermal treatment in the manufacturing process. As a result, an SOI semiconductor device in which an MOS capacitor on an SOI substrate offers performance comparable to an MOS capacitor on a silicon substrate can be formed.Type: GrantFiled: October 25, 2002Date of Patent: September 14, 2004Assignee: Denso CorporationInventor: Hiroyasu Itou
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Publication number: 20040070022Abstract: A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.Type: ApplicationFiled: September 12, 2003Publication date: April 15, 2004Inventors: Hiroyasu Itou, Mitsutaka Katada, Hidetoshi Muramoto
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Publication number: 20030094708Abstract: In a manufacturing process of an SOI structure semiconductor device in which an MOS capacitor is located on an SOI substrate, the capacitor insulating film of the MOS capacitor is prevented from degrading due to a bimetal effect, which is caused by a thermal treatment and characteristic to the SOI substrate. A trench is formed to surround the MOS capacitor in the SOI substrate, thick oxide films are formed on sidewalls defining the trench, and the trench is filled with polysilicon to complete a trench isolation layer. Because the thick oxide films have a coefficient of thermal expansion that is different from that of a silicon semiconductor layer of the SOI substrate, the thick oxide films are able to prevent the capacitor insulating film from degrading in film quality due to the thermal treatment in the manufacturing process. As a result, an SOI semiconductor device in which an MOS capacitor on an SOI substrate offers performance comparable to an MOS capacitor on a silicon substrate can be formed.Type: ApplicationFiled: October 25, 2002Publication date: May 22, 2003Inventor: Hiroyasu Itou
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Patent number: 6529788Abstract: A recycling system has a recycle information memory database for storing as recycle information, the information on all reutilizable products such as products produced or used under the management of the system, products treated as wastes, and products currently being used in the market. A virtual recycle product designing section is provided for estimating times when the reutilizable products are recovered as products usable for recycling as well as their volumes, based on the recycle information stored in the recycle information memory database. A production scheduling section is provided for setting a production schedule of a recycle product using the reutilizable products based on the estimated times and volumes.Type: GrantFiled: December 14, 1999Date of Patent: March 4, 2003Assignee: Ricoh Company, Ltd.Inventors: Tatsuo Tani, Kiyoshi Sakai, Yasushi Akiba, Shohzoh Miyawaki, Teruzo Hasumi, Mitsuaki Urakawa, Tetsuo Yamaoka, Hisashi Ishijima, Hiroyasu Itou
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Patent number: 6150697Abstract: An island region surrounded by a trench is provided in an SOI substrate. The island region is further surrounded by a buffer region with a buffer region contact layer. In the island region, a source region is annularly provided around a drain region, and source and drain electrodes are respectively provided on the source and the drain regions. An annular auxiliary electrode is formed with the source electrode to extend over the trench. Accordingly, a voltage applied to the source electrode can be applied to the auxiliary electrode, so that electric field concentration between the buffer region and the source electrode is relaxed.Type: GrantFiled: April 29, 1999Date of Patent: November 21, 2000Assignee: Denso CorporationInventors: Akihiko Teshigahara, Akiyoshi Asai, Kunihiro Onoda, Hiroyasu Itou, Ryuichirou Abe, Toshio Sakakibara
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Patent number: 5983059Abstract: A recyclable toner container having a hollow cylindrical body, a toner outlet at one end of the container, and a removable cap fitted in the toner outlet. The cap have a plurality of circumferential protuberances on an outer periphery thereof and contacting the inner periphery of the toner outlet. The diameters of the plurality of protuberances are sequentially increased from a downstream side toward an upstream side in a direction in which the cap is inserted into the toner outlet.Type: GrantFiled: September 8, 1997Date of Patent: November 9, 1999Assignee: Ricoh Company, Ltd.Inventors: Seiji Oka, Yasushi Akiba, Masumi Ikesue, Masakazu Nakada, Hiroyasu Itou
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Patent number: 5765087Abstract: The color image forming method of the kind sequentially forming toner images of different colors on an image carrier with developers of corresponding colors stored in a plurality of developing devices, sequentially transferring the toner images to a single paper or similar recording medium one above the other, and returning the toner left on the image carrier after the image transfer to the developing devices color by color, and an image forming apparatus practicable therewith. After the transfer of a toner image of any particular color to the paper wrapped around a transfer drum, a cleaning roller assigned to the above color each collects the toner remaining on the drum and again deposits it on the drum. The drum conveys the redeposited toner to one of the developing devices storing a developer of the same color as the toner.Type: GrantFiled: December 27, 1996Date of Patent: June 9, 1998Assignee: Ricoh Company, Ltd.Inventors: Hidetoshi Yano, Yasushi Nakazato, Takayuki Kimura, Masako Yoshii, Hiroyasu Itou
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Patent number: 5677208Abstract: An improved manufacturing method for a semiconductor device, which can reduce process inductive fault such as oxidation inductive stacking fault (OSF) and contribute to the improvement of the electric characteristics of the semiconductor device, is disclosed. A thermal oxide film is formed on a semiconductor substrate, then a nitride film is formed and a medium temperature heat treatment is provided to the semiconductor substrate within a temperature range from 600.degree. C. to 1,000.degree. C., whereby an interstitial oxygen concentration can be lowered. Subsequently, ion implantation, etc. are provided as a well region forming process, and a drive-in process is performed by means of a high temperature heat treatment. At this time, ion implantation dose is set to 9.times.10.sup.13 ?cm.sup.-2 ! or less, and the temperature of the heat treatment is lowered or the duration of the teat treatment is shortened.Type: GrantFiled: March 24, 1995Date of Patent: October 14, 1997Assignee: Nippondenso Co., Ltd.Inventors: Hiroyasu Itou, Hideya Inagaki
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Patent number: 5552342Abstract: An LOCOS film is formed on an Si substrate, a gate oxide film and a gate electrode are formed thereon, and source/drain impurities are ion implanted into the Si substrate using the gate electrode as a mask. Then, a BPSG film is formed at a film density of 1.8 g/cm.sup.3 or more. A recessed part is formed in the BPSG film by the first photolithographic process with an etching depth of 20% or more but under 100% of the thickness of the BPSG film. Thereafter, the BPSG film is fluidized by reflow treatment to shape a part which is to be a contact hole into a funnel with an "upwards convex" curvature. Finally, the part formed into the funnel is etched to make a contact hole. As a result, wiring disconnection within the contact hole can be prevented, the diffusion depth controllability for the source/drain impurities can be improved, and the fall in the impurity density in the source/drain surface can be prevented.Type: GrantFiled: August 19, 1994Date of Patent: September 3, 1996Assignee: Nippondenso Co., Ltd.Inventors: Hiroyasu Itou, Tosiyuki Morisita, Takanori Simamoto