Patents by Inventor Hiroyasu Jobetto

Hiroyasu Jobetto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8268674
    Abstract: A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: September 18, 2012
    Assignee: Teramikros, Inc.
    Inventor: Hiroyasu Jobetto
  • Patent number: 8237277
    Abstract: A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: August 7, 2012
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 8063490
    Abstract: A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: November 22, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Publication number: 20110233769
    Abstract: A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 29, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Hiroyasu JOBETTO
  • Patent number: 8004089
    Abstract: On the lower surface of a semiconductor construct having an external connection electrode, there are formed an insulating film having a planar size greater than that of the semiconductor construct, and a metal layer and a mask metal layer having a connection pad portion in which a first opening corresponding to the external connection electrode is formed. A laser beam is applied using the mask metal layer as a mask, and a second opening is thereby formed in a part of the insulating film corresponding to the external connection electrode. Then, a connection conductor is formed to connect a wiring line to the external connection electrode via the second opening of the insulating film.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: August 23, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 7972903
    Abstract: An insulating film covering the lower surface of an external connection electrode of a semiconductor construct is formed. A mask metal layer in which there is formed an opening having a planar size smaller than that of the external connection electrode is formed on the insulating film. The mask metal layer is used as a mask to apply a laser beam to the insulating film, such that a connection opening reaching the external connection electrode is formed in the insulating film. A wiring line is formed on the insulating film in such a manner as to be connected to the external connection electrode via the connection opening.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: July 5, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 7910405
    Abstract: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the semiconductor constructing body. An adhesion increasing film is formed between the insulating layer, and at least one of the semiconductor constructing body and the base member around the semiconductor constructing body, for preventing peeling between the insulating layer and the at least one of the semiconductor constructing body and base member.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: March 22, 2011
    Assignees: Casio Computer Co., Ltd., CMK Corporation
    Inventors: Osamu Okada, Hiroyasu Jobetto
  • Patent number: 7867828
    Abstract: A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: January 11, 2011
    Assignees: Casio Computer Co., Ltd., CMK Corporation
    Inventor: Hiroyasu Jobetto
  • Publication number: 20110001245
    Abstract: Disclosed in a semiconductor device including a semiconductor chip including an electrode, a projection electrode, an sealing film for encapsulating the semiconductor chip and the projection electrode, a first wiring lines provided on one surface of the sealing film, which is electrically connected with the electrode and the projection electrode, a second wiring lines provided on the other surface of the sealing film, which is electrically connected with the projection electrode and at least one of a first via hole conductor for electrically connecting the first wiring lines and the projection electrode or a second via hole conductor for electrically connecting the second wiring lines and the projection electrode, and an area of the projection electrode in an interface where the projection electrode and the first via hole conductor contact each other is greater than an area of the first via hole conductor in the interface and an area of the projection electrode in an interface where the projection electrode a
    Type: Application
    Filed: July 1, 2010
    Publication date: January 6, 2011
    Applicant: Casio Computer Co., Ltd.
    Inventor: Hiroyasu JOBETTO
  • Publication number: 20110001247
    Abstract: A semiconductor device manufacturing method comprises bonding a semiconductor element onto one surface of a first protective film via an adhesive layer, an electrode being formed in the semiconductor element, the first protective film being disposed on a first base material and including a first via hole, removing the first base material from the first protective film, applying first laser light to the adhesive layer through the first via hole to form a second via hole in the adhesive layer so that the electrode is exposed through the adhesive layer, and forming a metal layer in the second via hole to connect the metal layer to the electrode.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 6, 2011
    Applicant: Casio Computer Co., Ltd.
    Inventor: Hiroyasu JOBETTO
  • Publication number: 20100317154
    Abstract: A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed.
    Type: Application
    Filed: August 3, 2010
    Publication date: December 16, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 7843071
    Abstract: A semiconductor construct is provided which has a semiconductor substrate, an external connection electrode, and an electrode enveloping layer for enveloping the external connection electrode. Also, a base plate is provided which includes a wiring having a first opening corresponding to the external connection electrode. Subsequently, the base plate is removed after the semiconductor construct is fixed to the base plate, and a second opening which reaches the external connection electrode is formed on the electrode enveloping layer corresponding to the first opening of the wiring. Then, a connection conductor for electrically connecting the wiring and the external connection electrode is formed.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 30, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 7790515
    Abstract: A semiconductor device includes a semiconductor component which has a semiconductor substrate provided with an integrated circuit on an under side of the semiconductor substrate and a plurality of external connection electrodes provided on the underside of the semiconductor substrate, and a plurality of interconnections each of which includes one end portion connected to each of the external connection electrodes of the semiconductor component and the other end portion extended outside the semiconductor substrate. An under fill medium is provided to cover at least an underside of the semiconductor substrate and at least the side surfaces of the external connection electrodes. A sealing medium is provided to cover an upper side and a side surface of the semiconductor substrate, and the under fill medium. The undersurface of the under fill medium is flush with the undersurfaces of the interconnections.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: September 7, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Publication number: 20100193938
    Abstract: A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed.
    Type: Application
    Filed: March 23, 2010
    Publication date: August 5, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Hiroyasu JOBETTO
  • Patent number: 7737543
    Abstract: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: June 15, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Jobetto, Ichiro Mihara
  • Patent number: 7727862
    Abstract: A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: June 1, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 7709942
    Abstract: A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around the semiconductor constructing body, upper interconnections which are formed on the insulating layer and each includes at least one interconnection layer, at least some of the upper interconnections are connected to the external connection electrodes of the semiconductor constructing body, lower interconnections which are formed on the other surface of the base plate and each includes at least one interconnection layer, and at least some of the lower interconnections which are electrically connected to the upper interconnections.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: May 4, 2010
    Assignees: Casio Computer Co., Ltd., CMK Corporation
    Inventor: Hiroyasu Jobetto
  • Patent number: 7692282
    Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 6, 2010
    Assignee: Casio Computer Co., Ltd
    Inventors: Shinji Wakisaka, Hiroyasu Jobetto, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: RE41369
    Abstract: A semiconductor device includes at least one semiconductor structure having a plurality of external connection portions on an upper surface, and an insulating member which is made of a resin containing reinforcing materials and arranged on a side of the semiconductor structure. An insulating film is formed on the upper surface of the semiconductor structure, except the external connection portions, and on an upper surface of the insulating member. A plurality of upper wirings each of which has a connection pad portion are located on an upper side of the insulating film and electrically connected to a corresponding one of the external connection portions of the semiconductor structure. The connection pad portion of at least one of the upper wirings is arranged above an upper surface of the insulating member.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: June 8, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: RE43380
    Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: May 15, 2012
    Assignee: Teramikros, Inc.
    Inventors: Shinji Wakisaka, Hiroyasu Jobetto, Takeshi Wakabayashi, Ichiro Mihara