Patents by Inventor Hiroyasu Joubettou

Hiroyasu Joubettou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5736436
    Abstract: A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: April 7, 1998
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroshi Matsumoto, Haruo Wakai, Hiroyasu Joubettou
  • Patent number: 5545576
    Abstract: A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: August 13, 1996
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroshi Matsumoto, Haruo Wakai, Hiroyasu Joubettou