Abstract: A method for rewriting a semiconductor storage device includes: a first rewriting step of applying a pre-charge voltage to both of a plurality of bit lines and a plurality of source lines; a second rewriting step of applying a rewrite voltage to one of a selected bit line or a selected source line; a third rewriting step of applying a rewrite voltage to both of the selected bit line and the selected source line; a fourth rewriting step of applying a pre-charge voltage to one of the selected bit line or the selected source line; and a fifth rewriting step of applying a pre-charge voltage to both of the selected bit line and the selected source line.

Abstract: A semiconductor memory solves performance degradation of a memory device caused by performance of memory functions different depending on a position of a memory cell array. In the memory cell array including memory cells in each of which a memory element is electrically connected to one of a source and a drain of a cell transistor, the cell transistor includes at least two types with different current driving capability according to a position in the memory cell array.

Abstract: A method for rewriting a semiconductor storage device includes: a first rewriting step of applying a pre-charge voltage to both of a plurality of bit lines and a plurality of source lines; a second rewriting step of applying a rewrite voltage to one of a selected bit line or a selected source line; a third rewriting step of applying a rewrite voltage to both of the selected bit line and the selected source line; a fourth rewriting step of applying a pre-charge voltage to one of the selected bit line or the selected source line; and a fifth rewriting step of applying a pre-charge voltage to both of the selected bit line and the selected source line.

Abstract: A semiconductor memory solves performance degradation of a memory device caused by performance of memory functions different depending on a position of a memory cell array. In the memory cell array including memory cells in each of which a memory element is electrically connected to one of a source and a drain of a cell transistor, the cell transistor includes at least two types with different current driving capability according to a position in the memory cell array.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of reference cell arrays, a plurality of word lines, a plurality of bit lines, a plurality of reference word lines, a plurality of reference bit lines each being provided for an associated one of the reference cell arrays, and equalizing transistors each of which is provided between the plurality of reference bit lines and receives an associated one of independent control signals, and a potential of one of the plurality of reference bit lines and a plurality of one of the plurality of bit lines are input to a sense amplifier.

Abstract: A non-volatile semiconductor memory device includes a memory cell array including a data storage area and a reprogram information storage area, and a reprogram information holder circuit configured to store data read from the reprogram information storage area. A reference level switch circuit selects one from a plurality of read reference levels generated by a reference level generator circuit, based on an output of the reprogram information holder circuit. A read circuit reads memory cell data from the data storage area 104 based on the selected read reference level, and outputs the memory cell data. Therefore, a degradation in data hold capability due to reprogram operation is reduced or prevented. In addition, intended operation is achieved without being affected by interruption or resumption of power supply, a circuit size is reduced, and high-speed read operation is achieved.

Abstract: In order to determine data stored in a memory cell of a resistive cross-point cell array, two reference cells having two different known resistance values (e.g., data “0” and data “1”) are provided, and a difference in current between a selected cell and the reference cell having data “0” and a difference in current between the selected cell and the reference cell having data “1” are compared. By comparison with a current of the reference cell which has a parasitic current as with the selected cell and has known data “0”/“1”, data can be determined while suppressing an influence of a parasitic current.

Abstract: In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.

Abstract: In order to determine data stored in a memory cell of a resistive cross-point cell array, two reference cells having two different known resistance values (e.g., data “0” and data “1”) are provided, and a difference in current between a selected cell and the reference cell having data “0” and a difference in current between the selected cell and the reference cell having data “1” are compared. By comparison with a current of the reference cell which has a parasitic current as with the selected cell and has known data “0”/“1”, data can be determined while suppressing an influence of a parasitic current.

Abstract: In a nonvolatile memory cell having a trap layer, by executing first charge injection with a given wait time being secured and second charge injection after the first charge injection in a programming or erasing sequence, surrounding charge that may deteriorate the data retention characteristic is reduced utilizing an initial variation (charge loss phenomenon caused by binding of injected charge with the surrounding charge in an extremely short time) occurring immediately after programming. Thereafter, the charge loss in the initial variation is compensated, so that the subsequent data retention characteristic is improved. The second charge injection is executed only when a predetermined determination level has been reached.

Abstract: In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.