Abstract: For a program that runs on a microprocessor having a cache memory and an on-chip memory embedded therein with a capability of specifying and assigning embedded memory capacities, memory capacities to be allocated to the cache memory and the on-chip memory are determined according to memory sizes required for a set of referent data in the program, and a code is generated based on the memory capacities determined. The program may be divided by extracting at least one phase each comprised of a loop in the program and a set of referent data referred to in each phase, so that the memory capacities are determined according to the memory sizes required for the set of referent data divided.

Abstract: A pointer field compression/expansion method is provided for a computer system having a data structure reference function using a pointer. The pointers in data structure which a program refers to are classified into pointers to be frequently referred to and those not to be frequently referred to. The pointers not to be frequently referred to are determined as targets of compression and expansion to thereby reduce and suppress the overhead required for the pointer compression and expansion. Information indicating whether or not a pointer in data structure is a compression target is provided separately or such identifying information is embedded into in the pointer whereby the compressed or uncompressed format of the pointer can be dynamically determined.

Abstract: To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead, locality in data reference which cannot be detected by a conventional compiler is enabled to be detected by a user instruction or analysis by a compiler on the basis of a tendency that values of indices in an indirect reference array monotonously increase or decrease. By using the information, issuing of redundant prefetch instructions is suppressed, and data prefetching is enabled to be performed also on an indirect reference array.

Abstract: Under program execution environment, a file size of a heap dump is reduced which is acquired so as to detect memory leaks, and so as to investigate occurrence causes of the memory leaks. In order to provide a memory leak investigating means which can be used even in a large-scaled system, the below-mentioned heap dump acquiring method is provided: When a heap dump is acquired, only such an object within objects stored in a heap memory is outputted which is adapted to the following conditions: That is, in a condition (1), an object exists among objects which are newly produced within a designated time period, and in another condition (2), an object is present on a reference path defined from a root set to the object which satisfies the above-explained condition (1).

Abstract: A synchronous reference code indicative of the fact that synchronous updating was made is provided to data which is to be applied to a critical section, and the code is set when synchronous updating is made. After a sentence in the critical section is executed, it is confirmed whether or not the synchronous updating of the data was made. In a thread for synchronous reference, reference is made, it is confirmed whether or not synchronous updating was made, and then the correctness of the updating is confirmed. When the synchronous updating is not made, the execution of the critical section is completed. Thereby the simultaneous execution of the critical sections and reduction of an overhead are realized.

Abstract: To reduce labor required in investigating on a source of memory leaks with regard to the memory leaks generated in executing a program using a language which does not explicitly indicate release of data region. With regard to a plurality of data stored in a memory, relationship of data is grasped twice after an time interval therebetween. Next, increased data C1, E2, E3 which are not present in data of a first time are extracted from data of a second time, and weights “1”, “2”, “2” in accordance with data sizes are attached to the increased data. Next, the weights are successively propagated from a lower order data of a destination of reference to a higher order data of a source of reference successively.

Abstract: To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead, locality in data reference which cannot be detected by a conventional compiler is enabled to be detected by a user instruction or analysis by a compiler on the basis of a tendency that values of indices in an indirect reference array monotonously increase or decrease. By using the information, issuing of redundant prefetch instructions is suppressed, and data prefetching is enabled to be performed also on an indirect reference array.

Abstract: To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead, locality in data reference which cannot be detected by a conventional compiler is enabled to be detected by a user instruction or analysis by a compiler on the basis of a tendency that values of indices in an indirect reference array monotonously increase or decrease. By using the information, issuing of redundant prefetch instructions is suppressed, and data prefetching is enabled to be performed also on an indirect reference array.

Abstract: An interpreter for executing a programming language is equipped with a native code calling function. The interpreter calls native code and executes the native code by an emulation layer that performs emulation through hardware. The emulation layer monitors memory access instructions made by the native code to check if there are any illegal memory accesses, and manages information of execution states of portion of the native code, such that the execution states of the portion of the native code can be saved and restored.

Abstract: A processor for carrying out an arithmetic operation in accordance with a program using data stored in a memory connected to the outside includes: a register file having at least one register for storing therein data which is used in the arithmetic operation or data of the result of the arithmetic operation; a cache memory holding therein a copy of a part of the data which is stored in the memory; a hit/miss judgement circuit judging whether or not data which is to be accessed in accordance with an access instruction is present in the cache memory; and an arithmetic operation unit receiving as its input a judgement result obtained from the hit/miss judgement circuit and a data which has been read out from the register file to carry out a predetermined arithmetic operation.

Abstract: To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead, locality in data reference which cannot be detected by a conventional compiler is enabled to be detected by a user instruction or analysis by a compiler on the basis of a tendency that values of indices in an indirect reference array monotonously increase or decrease. By using the information, issuing of redundant prefetch instructions is suppressed, and data prefetching is enabled to be performed also on an indirect reference array.

Abstract: The present invention provides a memory access optimizing method which judges an access method suitable for each of memory accesses and executes the preload optimization and prefetch optimization, according to the judgement result, for an architecture equipped with a prefetch mechanism to write the data on a main storage device into a cache memory and a preload mechanism to write the data on the main storage device into a register without writing it into the cache memory. The memory access method judging step analyzes whether or not there is a designation of a memory access method by a user. Moreover, the memory access method judging step investigates whether or not the data are already in a cache memory, whether or not the data compete with other data for a cache, whether or not the data are to be referred to again later, and whether or not the data fulfill the restriction on register resources.

Abstract: Based on a repetitively executed program fragment like a loop in a source program, at least two patterns of object codes are generated which include object codes (a) using a speculative instruction and a speculative check instruction and an object codes (b) not using the speculative instruction and the speculative check instruction. Other object codes are generated that perform control transfer so that after the number of times a speculation failure is detected by the speculation check during the execution of the codes (a) satisfies a predetermined condition, the codes (b) are used for the subsequent repetitive execution.

Abstract: A nested-loop data prefetching method in which a program is converted so that prefetching is performed effectively even in nested loops in which the loop length of the innermost loops is short and the loop length of the outer loops is long. In this method, first a prefetch target loop is selected from the innermost loops in the nested loops. The selected loop is then split into a front half loop and a rear half loop by application of index set splitting. Further, an instruction to prefetch data used by the selected loop per se is inserted into the front half loop whereas an instruction to prefetch data used in the next prefetch target loop is inserted into the rear half loop.

Abstract: Prefetch instructions having a function to move data to a cache memory from main memory are scheduled simultaneously with execution of other instructions. The prefetch instructions are scheduled by replacing, with the original prefetch instructions, the virtual prefetch instructions obtained by unrolling a kernel section of the schedule constituted by generating a dependency graph having dependent relationships between the prefetch instruction and the memory reference instruction, and then applying the software pipelining thereto, or by further unrolling the kernel section of the constituted schedule to delete the redundant prefetch instructions, or further by applying the software pipelining to the dependency graph which is formed by combining a plurality of prefetch instructions and replacing the prefetch instructions with virtual prefetch instructions.

Abstract: In a processor system including a plurality of hardware resources, a method for arranging a program to suppress the power consumption by the resources includes the steps of determining which ones of the hardware resources are to be operated and from which instruction cycle to which instruction cycle to execute each instruction of the program; and based on the determination, adding an instruction to lower frequencies of clock signals inputted to the hardware resources and an instruction to restore the frequency at positions adjacent to the beginning and the end of the period during which the hardware resources are not operated and compiling the program. The processor system decodes the compiled program and lowers the frequency of the clock signal inputted to the hardware resources in accordance with the frequency lowering instruction and the frequency restoring instruction detected in the decoding step.