Abstract: A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.

Abstract: Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns 92 necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patterns 96 and 98 having different sizes are then designed in free regions not occupied by the functional patterns. While the dummy patterns are being designed, the largest possible number of free regions 94 are extracted followed by as many smaller free regions 97 as possible. The dummy patterns 98 are laid out in the extracted free regions.

Abstract: A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.

Abstract: Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns 92 necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patterns 96 and 98 having different sizes are then designed in free regions not occupied by the functional patterns. While the dummy patterns are being designed, the largest possible number of free regions 94 are extracted followed by as many smaller free regions 97 as possible. The dummy patterns 98 are laid out in the extracted free regions.

Abstract: A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.

Abstract: A method of manufacturing a semiconductor device having a memory device and a logic device on the same semiconductor substrate is provided without reducing reliability of the semiconductor device and making a manufacturing process unnecessarily complicated. A silicon oxide film which serves as a salicide protection film in the logic device formation region is subjected to wet isotropic etching. The process completely removes the silicon oxide film in the memory device formation region. Thus, the silicon oxide film is left only in a prescribed portion in the logic device formation region. As a result, the silicon oxide film is not left on an inner wall of a recess formed by a silicon nitride film between gate electrodes. Consequently, a good self alignment contact opening is formed toward a source/drain region in the memory device formation region.