Abstract: Data about display start positions are stored in an H register. An H start counter counts an original oscillation signal ORGCLK after the termination of a flyback period, and a comparator detects a start position. Flip flops and NOR gates form a clock having a cycle one and a half times as long as that of the original oscillation signal from the start position, and either the signal having a 1.5-fold cycle or the original oscillation signal is selected according to the level of a mode signal MODE. Thus, it is possible to obtain a clock OSDCLK having a frequency the same as that of the original oscillation signal up to the start position and a clock OSDCLK having a frequency corresponding to magnification from a display position. Therefore, by controlling display of characters based on the clock OSDCLK, display start positions can be made even regardless of magnification.

Abstract: Control data indicating the vertical start positions of display characters is written into the locations of a video RAM determined by a common column address and a plurality of column addresses. In each horizontal synchronizing period, all control data is read in sequence from the video RAM and set in sequence in a vertical start position register. A match is found between the contents of the vertical position counter indicating the current vertical position and the contents of the vertical start position register. When they match, after the horizontal synchronizing period, the video RAM is accessed with the control data as the vertical position start address.

Abstract: Specific clock periods in each machine cycle MC used by a CPU are used for accessing a video RAM synchronized with the operation of the operation of the CPU and the remaining clock periods of the machine cycle MC are used for accessing the video RAM synchronized with horizontal scanning and vertical scanning of television signal. Therefore, accessing synchronized with television signals is also performed in response to clock periods of a machine cycle MC and the video RAM can be made of a single port.

Abstract: An encoder disconnects video data between a video source and a video using device only during 21H in the vertical blanking interval. During 21H, it applies locally generated coded data signals, in a format detectable by conventional data decoding devices, to the video using device. The video source may be a camera or tape playback, and the using device may be a TV set or a video tape recorder.

Abstract: A channel display device in which a channel number which is receiving discrimination is flashed while a list of all channel numbers is displayed on a television screen. Also, a display color of the channel number discriminated as being in a receiving state is changed. Thus, a receivable channel from within a number of channels can be readily confirmed.