Patents by Inventor Hiroyasu Yoshida
Hiroyasu Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12272498Abstract: A multilayer ceramic capacitor includes a multilayer body including a laminate chip and side gap portions. The laminate chip includes an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and outer layer portions respectively on both sides of the inner layer portion in a lamination direction. Side gap portions are on both sides of the laminate chip in a width direction. The multilayer ceramic capacitor further includes external electrodes respectively on both sides of the multilayer body in a length direction. When a thickness of one of the outer layer portions is defined as T1, and a thickness of one of the side gap portions is defined as W1, W1 and T1 are about 20 ?m or less, and about 0.1<|(W1-T1)|/T1<about 0.3 is satisfied.Type: GrantFiled: October 18, 2021Date of Patent: April 8, 2025Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Hiroyasu Yoshida
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Publication number: 20220139631Abstract: A multilayer ceramic capacitor includes a multilayer body including a laminate chip and side gap portions. The laminate chip includes an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and outer layer portions respectively on both sides of the inner layer portion in a lamination direction. Side gap portions are on both sides of the laminate chip in a width direction. The multilayer ceramic capacitor further includes external electrodes respectively on both sides of the multilayer body in a length direction. When a thickness of one of the outer layer portions is defined as T1, and a thickness of one of the side gap portions is defined as W1, W1 and T1 are about 20 ?m or less, and about 0.1<|(W1-T1)|/T1<about 0.3 is satisfied.Type: ApplicationFiled: October 18, 2021Publication date: May 5, 2022Inventor: Hiroyasu YOSHIDA
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Patent number: 9484152Abstract: A substrate-type terminal includes a first major surface with a first mounting electrode and a second mounting electrode. The substrate-type terminal includes a second major surface with a first connecting electrode and a second connecting electrode. The substrate-type terminal includes a first slit located between the first mounting electrode and the first connecting electrode, as seen in a plane, and penetrating the terminal from the first major surface to the second major surface, and a second slit located between the second mounting electrode and the second connecting electrode, as seen in a plane, and penetrating the terminal from the first major surface to the second major surface.Type: GrantFiled: March 6, 2014Date of Patent: November 1, 2016Assignee: Murata Manufacturing Co., Ltd.Inventor: Hiroyasu Yoshida
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Publication number: 20140268487Abstract: A substrate-type terminal includes a first major surface with a first mounting electrode and a second mounting electrode. The substrate-type terminal includes a second major surface with a first connecting electrode and a second connecting electrode. The substrate-type terminal includes a first slit located between the first mounting electrode and the first connecting electrode, as seen in a plane, and penetrating the terminal from the first major surface to the second major surface, and a second slit located between the second mounting electrode and the second connecting electrode, as seen in a plane, and penetrating the terminal from the first major surface to the second major surface.Type: ApplicationFiled: March 6, 2014Publication date: September 18, 2014Applicant: Murata Manufacturing Co., Ltd.Inventor: Hiroyasu YOSHIDA
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Patent number: 8745454Abstract: When an update disable signal is at an inactivation level, a latch signal is activated in accordance with an active signal and a mode register set signal. When the update disable signal is at an activation level, the latch signal is activated in accordance with the active signal while being not activated in accordance with the mode register set signal. Based on the latch signal, the address signal is latched. Based on the latched address signal, an internal test signal is generated. With this structure, a target chip can be selectively controlled simply by activating the update disable signal in the target chip.Type: GrantFiled: November 9, 2011Date of Patent: June 3, 2014Inventor: Hiroyasu Yoshida
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Patent number: 8589964Abstract: Provided is a reliable optical pick-up which can prevent deterioration of a performance of a component, shortening of a service life or malfunctioning due to heat generation of an laser driver IC, wherein a metallic pattern is provided on a flexible printed board, having an area wider than the external shape of the laser driver IC and having an exposed outer surface, and made of the same material as that of a wiring pattern. It is preferable to bend the flexible printed board in a mounting part for the laser driver IC so that the metallic pattern is faced to and superposed with a surface of the flexible printed board on the side remote from the surface on which the laser driver IC is mounted.Type: GrantFiled: July 29, 2005Date of Patent: November 19, 2013Assignee: Hitachi Media Electronics Co., Ltd.Inventors: Manabu Ochi, Yukinari Ueki, Yoshitaka Kusano, Hiroyasu Yoshida, Fumihito Ichikawa
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Patent number: 8448197Abstract: To provide an optical pickup device adapted such that for adhesion fixing of a holder for holding an LD or a light-receiving element to an optical pickup casing via an ultraviolet-curable adhesive, curing shrinkage during ultraviolet irradiation can be reduced and adhesion fixing achieved with high positioning accuracy. In a structure for adhesion fixing of a holder for holding an LD or a light-receiving element to an optical pickup casing via an ultraviolet-curable adhesive, since protrusions are provided at peripheral sections (UV irradiation light source side) on a bonding surface of the holder, a section exposed to strong UV light is first cured, then after the adhesive has moved from an uncured section, the amount of shrinkage of the first cured section in a Z-direction is reduced, and the uncured section is cured.Type: GrantFiled: November 24, 2009Date of Patent: May 21, 2013Assignee: Hitachi Media Electronics Co., Ltd.Inventors: Hiroaki Furuichi, Kazumi Takahashi, Hiroyasu Yoshida
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Publication number: 20120131397Abstract: When an update disable signal is at an inactivation level, a latch signal is activated in accordance with an active signal and a mode register set signal. When the update disable signal is at an activation level, the latch signal is activated in accordance with the active signal while being not activated in accordance with the mode register set signal. Based on the latch signal, the address signal is latched. Based on the latched address signal, an internal test signal is generated. With this structure, a target chip can be selectively controlled simply by activating the update disable signal in the target chip.Type: ApplicationFiled: November 9, 2011Publication date: May 24, 2012Inventor: Hiroyasu YOSHIDA
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Patent number: 8169875Abstract: An optical pickup device includes a holder which holds an LD and a light-receiving element and an optical pickup case on which the holder is adhesively fixed via an ultraviolet cure adhesive, and is provided with a through hole on a bonding surface of the holder in order to reduce shrinkage when ultraviolet light is irradiated and to form a blind portion on which the ultraviolet light is not irradiated from a specific direction for adhesively fixing with high position accuracy.Type: GrantFiled: April 9, 2009Date of Patent: May 1, 2012Assignee: Hitachi Media Electronics Co., Ltd.Inventors: Hiroaki Furuichi, Yoshio Oozeki, Kazumi Takahashi, Taketoshi Moriyama, Hiroyasu Yoshida
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Publication number: 20120002779Abstract: A state detection circuit comprises: a first counter circuit that counts a series of first command signals indicative of start of an operation control; a second counter circuit that counts a series of second command signals indicative of completion of the operation control; a count coincidence detection circuit that detects coincidence between a count in the first counter circuit and a count in the second counter circuit; and a state storing circuit that is set by the series of first command signals and reset when coincidence is detected by the count coincidence detection circuit. The first and second counter circuits each comprise a binary counter.Type: ApplicationFiled: July 29, 2010Publication date: January 5, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Shintaro SHIMADA, Hiroyasu YOSHIDA
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Patent number: 7859933Abstract: A semiconductor memory device comprises an anti-fuse, a memory circuit including memory cells, and a peripheral circuit configured to access only an area of the memory circuit selected depending on a state of the anti-fuse.Type: GrantFiled: February 11, 2008Date of Patent: December 28, 2010Assignee: Elpida Memory, Inc.Inventors: Hiroyasu Yoshida, Kanji Oishi
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Patent number: 7830755Abstract: The present invention provides an optical head for realizing the stable operation by controlling the temperature of the semiconductor laser to a low level by reducing the heat transfer rate from a laser driver IC to a housing in the vicinity of a semiconductor laser, and an optical disc drive using the same. It provides an optical head having a semiconductor laser and a photo detector arranged on one side with respect to a straight line through the center of an object lens of an object lens actuator and in parallel to the axis contacted with bearings, and a laser driver IC arranged on the other side with respect to the straight line. Thereby, the distance from the laser driver IC to the semiconductor laser can sufficiently be ensured so that the heat transfer rate from the laser driver IC to the housing can be reduced.Type: GrantFiled: January 29, 2007Date of Patent: November 9, 2010Assignee: Hitachi Media Electronics Co., Ltd.Inventors: Manabu Ochi, Fumihito Ichikawa, Hiroyasu Yoshida, Mitsuo Satake
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Publication number: 20100162281Abstract: To provide an optical pickup device adapted such that for adhesion fixing of a holder for holding an LD or a light-receiving element to an optical pickup casing via an ultraviolet-curable adhesive, curing shrinkage during ultraviolet irradiation can be reduced and adhesion fixing achieved with high positioning accuracy. In a structure for adhesion fixing of a holder for holding an LD or a light-receiving element to an optical pickup casing via an ultraviolet-curable adhesive, since protrusions are provided at peripheral sections (UV irradiation light source side) on a bonding surface of the holder, a section exposed to strong UV light is first cured, then after the adhesive has moved from an uncured section, the amount of shrinkage of the first cured section in a Z-direction is reduced, and the uncured section is cured.Type: ApplicationFiled: November 24, 2009Publication date: June 24, 2010Applicant: HITACHI MEDIA ELECTRONICS CO., LTDInventors: Hiroaki FURUICHI, Kazumi TAKAHASHI, Hiroyasu YOSHIDA
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Publication number: 20090323498Abstract: An optical pickup device includes a holder which holds an LD and a light-receiving element and an optical pickup case on which the holder is adhesively fixed via an ultraviolet cure adhesive, and is provided with a through hole on a bonding surface of the holder in order to reduce shrinkage when ultraviolet light is irradiated and to form a blind portion on which the ultraviolet light is not irradiated from a specific direction for adhesively fixing with high position accuracy.Type: ApplicationFiled: April 9, 2009Publication date: December 31, 2009Inventors: Hiroaki Furuichi, Yoshio Oozeki, Kazumi Takahashi, Taketoshi Moriyama, Hiroyasu Yoshida
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Patent number: 7562269Abstract: A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and which improves testability of the semiconductor storage device. A plural number of holding circuits (103) are provided holding write data for memory cells of a memory cell array (101-1). The write data from the holding circuits (103) are written in the memory cells of the selected address. A plural number of comparators (CCMPN) are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted value or the inverted value of the write data held by the holding circuits (103) is output as the write data to the memory cells and as expectation data to the comparators (CCMPN) depending on the value of the inversion control signal (DIM).Type: GrantFiled: June 12, 2007Date of Patent: July 14, 2009Assignee: Elpida Memory, Inc.Inventors: Hiroyasu Yoshida, Kanji Oishi
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Patent number: 7492661Abstract: In a command generating circuit, operation mode signals (signals determining internal operations, such as ACTIVE, READ, WRITE, and PRECHARGE) are determined by decoding command signals /CS, /RAS, /CAS, and /WE. The operation mode signals and bank select signals (BS0, BS1, BS2, and BS3) are latched by internal clocks. Thereafter, a logical product (AND) of each of the latched operation mode signals and each of the latched bank select signals is calculated.Type: GrantFiled: January 9, 2007Date of Patent: February 17, 2009Assignee: Elpida Memory, Inc.Inventors: Hiroyasu Yoshida, Kanji Oishi
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Patent number: 7436729Abstract: A fuse circuit uses an electrically writable fuse circuit and comprises a first fuse unit provided with a first electrically writable fuse, and a second fuse unit provided with a second electrically writable fuse, and the state of logical add of the states of the first and second fuse units is used as the output of the electrically writable fuse circuit in the first and second fuse units. Reliability in writing in of the fuse can be improved by using such a fuse circuit for a redundancy decoder circuit or the like.Type: GrantFiled: October 4, 2005Date of Patent: October 14, 2008Assignee: Elpida Memory, Inc.Inventors: Hiroyasu Yoshida, Kanji Oishi, Naohisa Nishioka
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Publication number: 20080192558Abstract: A semiconductor memory device comprises an anti-fuse, a memory circuit including memory cells, and a peripheral circuit configured to access only an area of the memory circuit selected depending on a state of the anti-fuse.Type: ApplicationFiled: February 11, 2008Publication date: August 14, 2008Inventors: Hiroyasu Yoshida, Kanji Oishi
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Patent number: 7366143Abstract: The present invention aims to provide a radio base station that has equivalently high reception sensitivity without increasing the number of antenna elements while keeping the utilization efficiency of time slots high. The radio base station comprises a radio unit 101 and a radio unit 102. Two time slots, one at each radio unit, are allocated to a mobile station. After a signal transmitted from the mobile station is received and demodulated, a piece of data received by the radio unit 101 is compared with a piece of data received by the radio unit 102 so that one of the pieces of data that has fewer errors is selected.Type: GrantFiled: November 9, 2004Date of Patent: April 29, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Yasunori Akatsuka, Hiroyasu Yoshida, Daiki Takiguchi
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Publication number: 20080080358Abstract: The present invention provides an optical head for realizing the stable operation by controlling the temperature of the semiconductor laser to a low level by reducing the heat transfer rate from a laser driver IC to a housing in the vicinity of a semiconductor laser, and an optical disc drive using the same. It provides an optical head having a semiconductor laser and a photo detector arranged on one side with respect to a straight line through the center of an object lens of an object lens actuator and in parallel to the axis contacted with bearings, and a laser driver IC arranged on the other side with respect to the straight line. Thereby, the distance from the laser driver IC to the semiconductor laser can sufficiently be ensured so that the heat transfer rate from the laser driver IC to the housing can be reduced.Type: ApplicationFiled: January 29, 2007Publication date: April 3, 2008Inventors: Manabu OCHI, Fumihito Ichikawa, Hiroyasu Yoshida, Mitsuo Satake