Abstract: An information processing system includes a main memory, a request source, a data buffer, a memory request control unit, and a cache invalidation control unit. The request source generates a memory request to the main memory. The data buffer is provided between the request source and the main memory and temporarily stores memory request information from the request source. The memory request control unit reads out the memory request information from the data buffer to execute and control access of the main memory. The cache invalidation control unit controls cache invalidation processing with respect to the request source on the basis of the memory request information. The information processing system further includes a data read address buffer and a data buffer control unit. The data read address buffer stores a storage address of the memory request information in the data buffer. The data buffer control unit reads out the storage address in the data read address buffer to access the data buffer.