Patents by Inventor Hiroyoshi Ichikura

Hiroyoshi Ichikura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220319375
    Abstract: An operational amplifier has a first input terminal and an output terminal connected to a second input terminal of the operational amplifier, and output nodes connected to the source lines of a display panel. During a failure inspection mode, the connection between the output node and the output terminal of the operational amplifier included in another output circuit among one output circuit and the other output circuit is disconnected and the output node instead of the output terminal is connected to the second input terminal of the operational amplifier. A pair of source lines connected to the output nodes of the one output circuit and the other output circuit are linked to each other, and signals attained by acquiring and binarizing voltages outputted from the operational amplifier in the other output circuit as a monitor voltage at different timings are acquired as first and second failure determination signals.
    Type: Application
    Filed: March 14, 2022
    Publication date: October 6, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Hiroyoshi ICHIKURA
  • Publication number: 20220199048
    Abstract: A display driver drives a display device including a plurality of data lines and a demultiplexer. The demultiplexer includes a plurality of first switches connected to the respective plurality of data lines, and a series of driving voltages including a plurality of driving voltages is supplied via a first wiring. The demultiplexer supplies the plurality of driving voltages to the respective plurality of data lines via the plurality of first switches. The display driver includes: a voltage multiplexing part that generates the series of driving voltages; a second switch connected between the voltage multiplexing part and the first wiring; and a controller connected to the plurality of first switches and the second switch.
    Type: Application
    Filed: April 10, 2020
    Publication date: June 23, 2022
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyoshi ICHIKURA
  • Publication number: 20220172675
    Abstract: A display driving device includes a high voltage operating unit obtaining an operating current according to the application of the high power supply voltage from the first voltage application line; a low voltage operating unit that operates according to an application of a low power supply voltage to control the high voltage operating unit; a recycling circuit that receives the operating current from the high voltage operating unit via a relay coupling line and applies the low power supply voltage to the low voltage operating unit while supplying the received operating current to a reference potential line via the low voltage operating unit; and a current bypass circuit that flows a part of the operating current flowing through the relay coupling line into the reference potential line without supplying the part of the operating current to the recycling circuit according to a voltage increase in the low power supply voltage.
    Type: Application
    Filed: March 30, 2020
    Publication date: June 2, 2022
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyoshi ICHIKURA
  • Patent number: 11011111
    Abstract: A display driving device comprising: a high supply voltage operation unit that generates an operating current under application of a high supply voltage so as to supply driving voltages to a display panel; a low supply voltage operation unit that operates under the application of a low supply voltage lower than the high supply voltage and controls the high supply voltage operation unit; and a reuse circuit that receives the operating current from the high supply voltage operation unit and supplies the operating current to a ground side via the low supply voltage operation unit so as to apply the low supply voltage to the low supply voltage operation unit.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 18, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyoshi Ichikura, Hiroki Aizawa, Takeshi Nosaka
  • Publication number: 20200184891
    Abstract: A display driving device comprising: a high supply voltage operation unit that generates an operating current under application of a high supply voltage so as to supply driving voltages to a display panel; a low supply voltage operation unit that operates under the application of a low supply voltage lower than the high supply voltage and controls the high supply voltage operation unit; and a reuse circuit that receives the operating current from the high supply voltage operation unit and supplies the operating current to a ground side via the low supply voltage operation unit so as to apply the low supply voltage to the low supply voltage operation unit.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroyoshi ICHIKURA, Hiroki AIZAWA, Takeshi NOSAKA
  • Patent number: 10580357
    Abstract: A display driving device comprising: a high supply voltage operation unit that generates an operating current under application of a high supply voltage so as to supply driving voltages to a display panel; a low supply voltage operation unit that operates under the application of a low supply voltage lower than the high supply voltage and controls the high supply voltage operation unit; and a reuse circuit that receives the operating current from the high supply voltage operation unit and supplies the operating current to a ground side via the low supply voltage operation unit so as to apply the low supply voltage to the low supply voltage operation unit.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 3, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyoshi Ichikura, Hiroki Aizawa, Takeshi Nosaka
  • Publication number: 20190237012
    Abstract: A display driving device comprising: a high supply voltage operation unit that generates an operating current under application of a high supply voltage so as to supply driving voltages to a display panel; a low supply voltage operation unit that operates under the application of a low supply voltage lower than the high supply voltage and controls the high supply voltage operation unit; and a reuse circuit that receives the operating current from the high supply voltage operation unit and supplies the operating current to a ground side via the low supply voltage operation unit so as to apply the low supply voltage to the low supply voltage operation unit.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 1, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroyoshi ICHIKURA, Hiroki AIZAWA, Takeshi NOSAKA
  • Patent number: 10121721
    Abstract: A dummy bump electrode for heat-dissipating is provided on a surface of a semiconductor chip. The semiconductor chip is mounted on a wiring substrate. A lead line is formed on the wiring substrate. The heat-dissipating bump electrode and a lead line are connected to each other through a heat dissipation pattern, thereby efficiency of the heat dissipation is improved.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 6, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Ichikura
  • Patent number: 9666143
    Abstract: An amplifying circuit includes a first differential amplifier (first differential pair) and a second differential amplifier (second differential pair) having an input capacitance smaller than the first differential amplifier. The amplifying circuit switches between the first differential amplifier (first differential pair) and the second differential amplifier (second differential pair) in response to an amplification mode setting signal to perform amplification processing of an input signal.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: May 30, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyoshi Ichikura, Koji Higuchi
  • Patent number: 9537505
    Abstract: A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: January 3, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyoshi Ichikura, Kunihiro Harayama, Hideaki Hasegawa
  • Publication number: 20160172269
    Abstract: A dummy bump electrode for heat-dissipating is provided on a surface of a semiconductor chip. The semiconductor chip is mounted on a wiring substrate. A lead line is formed on the wiring substrate. The heat-dissipating bump electrode and a lead line are connected to each other through a heat dissipation pattern, thereby efficiency of the heat dissipation is improved.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 16, 2016
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyoshi ICHIKURA
  • Publication number: 20160079926
    Abstract: An amplifying circuit includes a first differential amplifier (first differential pair) and a second differential amplifier (second differential pair) having an input capacitance smaller than the first differential amplifier. The amplifying circuit switches between the first differential amplifier (first differential pair) and the second differential amplifier (second differential pair) in response to an amplification mode setting signal to perform amplification processing of an input signal.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 17, 2016
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroyoshi ICHIKURA, Koji HIGUCHI
  • Publication number: 20160072522
    Abstract: A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 10, 2016
    Inventors: Hiroyoshi ICHIKURA, Kunihiro HARAYAMA, Hideaki HASEGAWA
  • Patent number: 9070340
    Abstract: There is provided a driving device of a display device, including: a first switching portion; a second switching portion; and a control section that, when the potential of a drive signal line is lower than a target potential, operates the first switching portion by using, as a first reference potential, a potential that is less than or equal to the target potential and that is closest to the target potential, among predetermined n types (n?1) of potentials, and, when the potential of the drive signal line is higher than the target potential, operates the second switching portion by using, as a second reference potential, a potential that is greater than or equal to the target potential and that is closest to the target potential, among the n types of potentials.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: June 30, 2015
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hideaki Hasegawa, Hiroyoshi Ichikura, Kazuhide Aoyama
  • Patent number: 8736642
    Abstract: An offset-reducing output circuit of a source driver adapted to drive a liquid crystal device. The output circuit includes an operational amplifier having a non-inverting input to receive a reference voltage. The output circuit also includes input and output capacitors. One terminal of the input capacitor and one terminal of the output capacitor are connected to a node extending to an inverting input of the operational amplifier in at least a normal output operation mode. The output circuit also includes a switching circuit to short both terminals of the input capacitor and both terminals of the output capacitor in a reset operation so that the reference voltage is applied to the terminals of the input and output capacitors respectively. The switching device applies a gray scale voltage to an opposite terminal of the input capacitor in a normal operation mode.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: May 27, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Hiroyoshi Ichikura, Koji Yamazaki
  • Patent number: 8729961
    Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 20, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Ichikura
  • Patent number: 8692355
    Abstract: A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 8, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Daisuke Tanaka, Hiroyoshi Ichikura
  • Patent number: 8477159
    Abstract: An offset cancel output circuit of source drivers for driving liquid crystal displays which is capable of appropriately cancelling out an offset voltage from an output amplifier to thereby prevent degradation in display quality. The offset cancel output circuit includes an operational amplifier with a non-inverted input port to which a reference voltage is applied, and an input capacitor and an output capacitor with each one end thereof connected to an inverted input port of the operational amplifier. The offset cancel output circuit further includes a switching element circuit which has a first field effect transistor connected between the inverted input port and an output port of the operational amplifier and controlled to turn on during a reset operation. During the reset operation and the normal output operation, a first potential equal to the reference voltage is applied to the substrate of the first field effect transistor.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 2, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Ichikura
  • Patent number: 8384473
    Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 26, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Ichikura
  • Publication number: 20120306571
    Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 6, 2012
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyoshi ICHIKURA