Abstract: According to the present embodiment, a semiconductor device includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

Abstract: According to the present embodiment, a semiconductor device includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

Abstract: A semiconductor device includes first to sixth transistors of enhancement type. The first and fourth transistors are of p-channel type. The second, third, fifth and sixth transistors are of n-channel type. A breakdown voltage of the third transistor is lower than a breakdown voltage of the second transistor. A breakdown voltage of the sixth transistor is lower than a breakdown voltage of the fifth transistor. The first to third transistors are connected in series between a first power supply potential and a second power supply potential lower than the first power supply potential. The fourth to sixth transistors are connected in series between the first power supply potential and the second power supply potential.

Abstract: A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.

Abstract: A semiconductor device includes first to sixth transistors of enhancement type. The first and fourth transistors are of p-channel type. The second, third, fifth and sixth transistors are of n-channel type. A breakdown voltage of the third transistor is lower than a breakdown voltage of the second transistor. A breakdown voltage of the sixth transistor is lower than a breakdown voltage of the fifth transistor. The first to third transistors are connected in series between a first power supply potential and a second power supply potential lower than the first power supply potential. The fourth to sixth transistors are connected in series between the first power supply potential and the second power supply potential.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.

Abstract: A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.

Abstract: A semiconductor device includes a semiconductor portion of a first conductivity type, a first semiconductor layer and a second semiconductor layer of a second conductivity type separated from each other and provided in an upper layer portion of the semiconductor portion, a gate electrode provided on the semiconductor portion, a first contact piercing the gate electrode, a second contact piercing the gate electrode, a first insulating film provided between the first semiconductor layer and a side surface of the first contact and between the first contact and the gate electrode, and a second insulating film provided between the second semiconductor layer and a side surface of the second contact and between the second contact and the gate electrode. A lower portion of the first contact is disposed inside the first semiconductor layer, a lower end of the first contact is connected to the first semiconductor layer.

Abstract: A semiconductor device includes a semiconductor portion of a first conductivity type, a first semiconductor layer and a second semiconductor layer of a second conductivity type separated from each other and provided in an upper layer portion of the semiconductor portion, a gate electrode provided on the semiconductor portion, a first contact piercing the gate electrode, a second contact piercing the gate electrode, a first insulating film provided between the first semiconductor layer and a side surface of the first contact and between the first contact and the gate electrode, and a second insulating film provided between the second semiconductor layer and a side surface of the second contact and between the second contact and the gate electrode. A lower portion of the first contact is disposed inside the first semiconductor layer, a lower end of the first contact is connected to the first semiconductor layer.

Abstract: A semiconductor device includes at least one memory cell including a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, which is a source region of the memory cell, over a portion of the first semiconductor region, and a second conductivity type third semiconductor region, which is a drain region of the memory cell, over a portion of the first semiconductor region spaced from the second semiconductor region in a first direction, a gate insulating layer extending over a channel region of the memory cell, which includes a portion of the first semiconductor region between the second and third semiconductor regions, and including a first portion of first thickness and a second portion of second thickness less than the first thickness, an electrically floating gate electrode on the gate insulating layer, and a control gate adjacent to, and spaced from, the electrically floating gate electrode.

Abstract: A semiconductor device has an insulating film and an n-type buried layer. The insulating film is formed in a flat-shaped cavity formed inside a p-type semiconductor substrate and in a trench extending from a surface of the semiconductor substrate to the cavity. The buried layer is formed in surrounding regions of the cavity and the trench in the semiconductor substrate.