Abstract: An area for layout of a plurality of I/O cells (called an “I/O area”) is provided in the peripheral portion of a chip and signal wirings for transferring test signals to the I/O cells are provided in the layout direction of the I/O cells. At least one empty cell provided in the I/O area at a position where I/O cells are not provided has a repeater circuit which constitutes a transfer path for the test signal. The repeater circuit receives the test signal and outputs the test signal. This structure provides a suitable semiconductor integrated circuit device adaptable for an ASIC or the like, which can adjust the delay of a test signal to be transferred along the chip's peripheral portion by suppressing an increase in the delay and degradation in waveform depression.

Abstract: An area for layout of a plurality of I/O cells (called “I/O area”) is provided in the peripheral portion of a chip and signal wirings for transfer a test signal to the I/O cells are provided in the layout direction of the I/O cells. At least one of empty cells provided in the I/O area at positions where the I/O cells are not provided has a repeater circuit which constitutes a transfer path for the test signal. The repeater circuit receives the test signal and outputs the test signal. This structure provides a suitable semiconductor integrated circuit device adaptable for ASIC or so, which can adjust the delay of a test signal to be transferred along the chip's peripheral portion by suppressing an increase in the delay and degradation in waveform depression.

Abstract: A simulation method of performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit, on the basis of a positional relationship between transistors, well contact interconnections, and sub-contact interconnections of the layout data. Parasitic resistances and parasitic capacitances in conductive regions between sub-terminals of the transistors are evaluated. A simulation apparatus for performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit is also disclosed.