Abstract: When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.

Abstract: A first switch operates in accordance with a control signal and receives an input signal. A voltage conversion circuit converts the input signal having a voltage and transmitted via the first switch to an output signal having a different voltage, and outputs the signal. A second switch connects an output node thereof to a voltage line supplied with a voltage which the voltage conversion circuit should output in accordance with the input signal. Therefore, even the input signal's voltage falling outside the range in which the voltage conversion circuit normally operates, the voltage that the voltage conversion circuit should intrinsically output is supplied to the output node via the second switch. Thus, reliable conversion of the input signal voltage is achieved, resulting in secure operation of the level shifter even during a low power supply voltage. This also prevents malfunction of the semiconductor integrated circuit incorporating such level shifters.

Abstract: A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.

Abstract: When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.

Abstract: A first switch operates in accordance with a control signal and receives an input signal. A voltage conversion circuit converts the input signal having a voltage and transmitted via the first switch to an output signal having a different voltage, and outputs the signal. A second switch connects an output node thereof to a voltage line supplied with a voltage which the voltage conversion circuit should output in accordance with the input signal. Therefore, even the input signal's voltage falling outside the range in which the voltage conversion circuit normally operates, the voltage that the voltage conversion circuit should intrinsically output is supplied to the output node via the second switch. Thus, reliable conversion of the input signal voltage is achieved, resulting in secure operation of the level shifter even during a low power supply voltage. This also prevents malfunction of the semiconductor integrated circuit incorporating such level shifters.

Abstract: A semiconductor memory device which includes at least two memory cell arrays, a sense amplifier shared by the memory cell arrays and at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier. The semiconductor memory device further includes a first voltage supplier supplying a first voltage to the transfer gates, and a second voltage supplier supplying a second voltage to the transfer gates, with second voltage being higher than the first voltage.

Abstract: A semiconductor memory device is provided. The semiconductor memory device comprises at least two memory cell arrays, a sense amplifier shared by the memory cell arrays, at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier, a first voltage supplier supplying a first voltage to the transfer gates, and a second voltage supplier supplying a second voltage to the transfer gates. The second voltage is higher than the first voltage.

Abstract: A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.