Patents by Inventor Hiroyoshi Urushihata

Hiroyoshi Urushihata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056422
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 6, 2021
    Assignees: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Publication number: 20210134709
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region an an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Application
    Filed: May 29, 2018
    Publication date: May 6, 2021
    Applicants: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
  • Patent number: 10784186
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 22, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10777489
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 15, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10600725
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 24, 2020
    Assignees: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Publication number: 20190371709
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic
    Type: Application
    Filed: October 16, 2018
    Publication date: December 5, 2019
    Applicant: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
  • Publication number: 20190371712
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Application
    Filed: October 16, 2018
    Publication date: December 5, 2019
    Applicant: Katoh Electric Co., Ltd.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Publication number: 20190371710
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first dip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame and a sealing resin.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 5, 2019
    Applicants: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
  • Patent number: 8399970
    Abstract: When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: March 19, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Hiroyoshi Urushihata
  • Publication number: 20110316135
    Abstract: When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided.
    Type: Application
    Filed: June 29, 2011
    Publication date: December 29, 2011
    Applicant: ON Semiconductor Trading, Ltd.
    Inventor: Hiroyoshi URUSHIHATA
  • Patent number: 7968983
    Abstract: Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor elements (a first and a second semiconductor elements) that are packaged in the semiconductor device are overlaid with each other. Specifically, the first semiconductor element is fixed on the top surface of the first island while the second semiconductor element is fixed on the bottom surface of the second island. Furthermore, each of the islands (a first and a second islands) on which the semiconductor elements are respectively mounted in the present invention provides a structure has an irregular shape, and the islands are overlaid with each other along the sides of the semiconductor element to be mounted.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: June 28, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Urushihata
  • Patent number: 7800206
    Abstract: Provided is a semiconductor device which is small in size and in which the deformation of leads is prevented at the time of wire-bonding. The semiconductor device includes: an island; a semiconductor element mounted on the bottom surface of the island; leads provided close to the island; and a sealing resin for integrally sealing these constituents. Moreover, in the semiconductor device according to the present invention, electrodes on the semiconductor element are bonded to the leads provided adjacent to a side of the island, the side not provided with leads which extends continuously from the island.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: September 21, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Hiroyoshi Urushihata
  • Publication number: 20080284008
    Abstract: Provided is a semiconductor device which is small in size and in which the deformation of leads is prevented at the time of wire-bonding. The semiconductor device includes: an island; a semiconductor element mounted on the bottom surface of the island; leads provided close to the island; and a sealing resin for integrally sealing these constituents. Moreover, in the semiconductor device according to the present invention, electrodes on the semiconductor element are bonded to the leads provided adjacent to a side of the island, the side not provided with leads which extends continuously from the island.
    Type: Application
    Filed: September 26, 2007
    Publication date: November 20, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyoshi Urushihata
  • Publication number: 20080251899
    Abstract: Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor elements (a first and a second semiconductor elements) that are packaged in the semiconductor device are overlaid with each other. Specifically, the first semiconductor element is fixed on the top surface of the first island while the second semiconductor element is fixed on the bottom surface of the second island. Furthermore, each of the islands (a first and a second islands) on which the semiconductor elements are respectively mounted in the present invention provides a structure has an irregular shape, and the islands are overlaid with each other along the sides of the semiconductor element to be mounted.
    Type: Application
    Filed: September 26, 2007
    Publication date: October 16, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyoshi Urushihata