Abstract: A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.

Abstract: A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.

Abstract: A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.

Abstract: A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.

Abstract: An external port control register of an input/output port outputs a setting value signal indicating a setting value in order that either a general-purpose input/output port function or a functional block input/output pin function is set to an external pin. A selector of the input/output port connects either a general output path or an output path of a functional block receiving a functional block input signal, to the external pin according to the setting value signal. An interrupting circuit interrupts the supply of the functional block input signal to the functional block when the setting value signal indicates the general-purpose input/output port function. Consequently, any register circuit designating whether to enable or disable the supply of the functional block input signal to the functional block need not be provided in particular, which can eliminate the need for a redundant setting process in switching the pin function of the external pin.

Abstract: This invention relates to switching-over to a higher speed clock from a lower speed clock. The switching-over of the clock is performed before, after, or simultaneously to a transition to a sleep mode is carried out. After the switching-over of the clock is performed, if oscillation of the high speed clock and an internal voltage are stabilized, it is returned to a normal mode from the sleep mode.

Abstract: The present invention provides a microprocessor capable of improving the throughput of a CPU. Module like the program ROMs in which instruction accesses are concentrated by a CPU are put together in a first Princeton bus, and modules like the external bus I/F, SDRAM I/F, peripheral bus I/F in which data accesses are mainly concentrated are put together in a second Princeton bus. Therefore, the instruction access and the data access can be carried out in parallel with respect to the buses of the instruction bus and the data bus individually through a bus control unit. Because the buses can be used efficiently, the throughput of the CPU can be improved substantially.

Abstract: This invention relates to switching-over to a higher speed clock from a lower speed clock. The switching-over of the clock is performed before, after, or simultaneously to a transition to a sleep mode is carried out. After the switching-over of the clock is performed, if oscillation of the high speed clock and an internal voltage are stabilized, it is returned to a normal mode from the sleep mode.