Patents by Inventor Hiroyuki Arie

Hiroyuki Arie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014067
    Abstract: A semiconductor device having a semiconductor substrate, a BOX film on the semiconductor substrate, a semiconductor layer on the BOX film, a first trench penetrated through the semiconductor layer and reached to the first insulating film, a first insulating film covering a side surface of the first trench and in contact with an upper surface of the BOX film at a bottom of the first trench, a second trench formed at the bottom of the first trench such that the second trench penetrates through the first insulating film and reached in the BOX film, a second insulating film filled in the first trench and the second trench. A bottom surface of the second trench is located in the BOX film below an interface between the semiconductor layer and the BOX film, and a void is located in the second insulating film at the same height the interface.
    Type: Application
    Filed: May 17, 2023
    Publication date: January 11, 2024
    Inventors: Hiroyuki ARIE, Takayuki IGARASHI
  • Patent number: 9437644
    Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 6, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi Eikyu, Atsushi Sakai, Hiroyuki Arie
  • Publication number: 20150130009
    Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 14, 2015
    Inventors: Katsumi EIKYU, Atsushi SAKAI, Hiroyuki ARIE
  • Publication number: 20120302061
    Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
    Type: Application
    Filed: August 1, 2012
    Publication date: November 29, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki ARIE, Nobuaki UMEMURA, Nobuyoshi HATTORI, Nobuto NAKANISHI, Kimio HARA, Kyoya NITTA, Makoto ISHIKAWA
  • Patent number: 8242605
    Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Arie, Nobuaki Umemura, Nobuyoshi Hattori, Nobuto Nakanishi, Kimio Hara, Kyoya Nitta, Makoto Ishikawa
  • Publication number: 20100327349
    Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 30, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki ARIE, Nobuaki UMEMURA, Nobuyoshi HATTORI, Nobuto NAKANISHI, Kimio HARA, Kyoya NITTA, Makoto ISHIKAWA