Patents by Inventor Hiroyuki Deai

Hiroyuki Deai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220009783
    Abstract: The purpose of the present invention is to provide: silica particles of which the maximum particle diameter can be minimized and which can achieve proper fluidability that cannot be achieved by the conventional techniques; and silica spherical particles which, when used as a filler for a heat-dissipating sheet, can achieve excellent heat conductivity and flexibility. Silica spherical particles characterized in that, when particles each having a size of 5 ?m or more and imaged by an optical measurement are observed, the particle diameter of each of the particles, which is determined from the image, satisfies the following requirements. Requirements: D99?29 ?m, and 10 ?m?Dmode<D99, and D99/Dmode?1.5, and Dmode?20 ?m.
    Type: Application
    Filed: November 13, 2019
    Publication date: January 13, 2022
    Applicant: NIPPON STEEL Chemical & Material Co., Ltd.
    Inventors: Katsumasa YAGI, Dota SAITO, Mutsuhito TANAKA, Masanori AE, Hiroyuki DEAI
  • Patent number: 10950570
    Abstract: There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. The bonding wire for a semiconductor includes a Cu alloy core material, and a Pd coating layer formed on a surface of the Cu alloy core material, and is characterized in that the Cu alloy core material contains Ni, a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, and a thickness of the Pd coating layer is 0.015 to 0.150 ?m.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: March 16, 2021
    Assignees: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD., NIPPON MICROMETAL CORPORATION
    Inventors: Tetsuya Oyamada, Tomohiro Uno, Hiroyuki Deai
  • Patent number: 10526722
    Abstract: The present invention provides a method of manufacturing by the sublimation-recrystallization method more accurately detecting a thermal state of a starting material in a crucible and enabling control of the growth conditions while manufacturing an SiC single crystal.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 7, 2020
    Assignee: SHOWA DENKO K.K.
    Inventors: Masashi Nakabayashi, Kiyoshi Kojima, Hiroyuki Deai, Kota Shimomura, Yukio Nagahata
  • Patent number: 10381320
    Abstract: The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: August 13, 2019
    Assignees: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD., NIPPON MICROMETAL CORPORATION
    Inventors: Tetsuya Oyamada, Tomohiro Uno, Hiroyuki Deai, Daizo Oda
  • Publication number: 20180251909
    Abstract: The present invention provides a method of manufacturing by the sublimation-recrystallization method more accurately detecting a thermal state of a starting material in a crucible and enabling control of the growth conditions while manufacturing an SiC single crystal.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 6, 2018
    Applicants: NIPPON STEEL & SUMITOMO METAL CORPORATION, NIPPON STEEL & SUMIKIN MATERIALS CO., LTD.
    Inventors: Masashi NAKABAYASHI, Kiyoshi KOJIMA, Hiroyuki DEAI, Kota SHIMOMURA, Yukio NAGAHATA
  • Publication number: 20170110430
    Abstract: The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.
    Type: Application
    Filed: May 20, 2015
    Publication date: April 20, 2017
    Inventors: Tetsuya OYAMADA, Tomohiro UNO, Hiroyuki DEAI, Daizo ODA
  • Publication number: 20170040281
    Abstract: There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. The bonding wire for a semiconductor includes a Cu alloy core material, and a Pd coating layer formed on a surface of the Cu alloy core material, and is characterized in that the Cu alloy core material contains Ni, a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, and a thickness of the Pd coating layer is 0.015 to 0.150 ?m.
    Type: Application
    Filed: April 21, 2015
    Publication date: February 9, 2017
    Inventors: Tetsuya OYAMADA, Tomohiro UNO, Hiroyuki DEAI
  • Publication number: 20120032229
    Abstract: A silicon wafer contains: a silicon substrate; a first epitaxial layer on the silicon wafer, wherein the absolute value of the difference between donor and acceptor concentrations is ?1×1018 atoms/cm3; a second epitaxial layer above the first epitaxial layer, whose conductivity type is the same as the first epitaxial layer, wherein the absolute value of the difference between donor and acceptor concentrations is ?5×1017 atoms/cm3; wherein, by doping a lattice constant adjusting material into the first epitaxial layer, the variation amount ((a1-aSi)/aSi) of the lattice constant of the first epitaxial layer (a1) relative to the lattice constant of the silicon single crystal (aSi) as well as the variation amount ((a2-aSi)/aSi) of the lattice constant of the second epitaxial layer (a2) relative to the lattice constant of the silicon single crystal (aSi) are controlled to less than the critical lattice mismatch.
    Type: Application
    Filed: July 27, 2011
    Publication date: February 9, 2012
    Applicant: SILTRONIC AG
    Inventors: Hiroyuki Deai, Seiji Takayama
  • Patent number: 8043929
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: October 25, 2011
    Assignee: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried von Ammon
  • Publication number: 20080268613
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Application
    Filed: May 14, 2008
    Publication date: October 30, 2008
    Applicant: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried von Ammon
  • Publication number: 20050139961
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 30, 2005
    Applicant: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried Ammon