Patents by Inventor Hiroyuki Dohmae
Hiroyuki Dohmae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014061Abstract: According to one embodiment, a cassette housing includes a storage unit, a probe card, and a container. The storage unit stores a semiconductor wafer including a plurality of nonvolatile memory chips. The probe card includes a probe. The probe is configured to be brought into contact with a pad electrode provided on the semiconductor wafer. The container contains heat transfer fluid for lowering or raising temperature of one or both of the probe card and the semiconductor wafer stored in the storage unit.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Inventors: Tatsuro HITOMI, Yasuhito YOSHIMIZU, Arata INOUE, Hiroyuki DOHMAE, Kazuhito HAYASAKA, Tomoya SANUKI
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Publication number: 20240014062Abstract: According to one embodiment, when a first case-mounted memory device that includes a first memory device is not connected to a slot of a host apparatus and is stored in a second stocker, the host apparatus causes a second transport device to transport the first case-mounted memory device to the slot, and to connect it thereto. When the first case-mounted memory device is not connected to the slot and is not stored in the second stocker, the host apparatus causes a first transport device to transport the first memory device from a first stocker to a mounter, causes the mounter to mount the first memory device in a case, and causes the second transport device to transport the first case-mounted memory device to the slot and to connect it thereto.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Inventors: Tatsuro HITOMI, Yasuhito YOSHIMIZU, Arata INOUE, Hiroyuki DOHMAE, Kazuhito HAYASAKA, Tomoya SANUKI
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Publication number: 20230324455Abstract: According to one embodiment, a wafer includes a substrate including a first region and a second region that do not overlap each other; a first chip unit and a second chip unit each arranged on the substrate; a first electrode and a second electrode each electrically connected to the first chip unit; and a third electrode and a fourth electrode each electrically connected to the second chip unit. The first electrode and the third electrode are arranged in the first region. The second electrode and the fourth electrode are arranged in the second region. The first region is independent of a region in which the first chip unit and the second chip unit are provided.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Inventors: Tatsuro HITOMI, Yasuhito YOSHIMIZU, Masayuki MIURA, Arata INOUE, Hiroyuki DOHMAE, Koichi NAKAZAWA, Mitoshi MIYAOKA, Kazuhito HAYASAKA, Tomoya SANUKI
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Patent number: 7515473Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: GrantFiled: September 27, 2007Date of Patent: April 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae
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Patent number: 7400531Abstract: A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops spent for data write to several memory cells, and outputs the accumulated and stored number of program loops.Type: GrantFiled: June 16, 2006Date of Patent: July 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ohtake, Hiroyuki Dohmae
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Patent number: 7394704Abstract: A non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: GrantFiled: November 30, 2005Date of Patent: July 1, 2008Assignees: Kabushiki Kaisha Toshiba, Sandisk CorporationInventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
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Publication number: 20080025101Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: ApplicationFiled: September 27, 2007Publication date: January 31, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae
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Patent number: 7277325Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: GrantFiled: April 28, 2006Date of Patent: October 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae
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Publication number: 20070002638Abstract: A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops spent for data write to several memory cells, and outputs the accumulated and stored number of program loops.Type: ApplicationFiled: June 16, 2006Publication date: January 4, 2007Inventors: Hiroyuki Ohtake, Hiroyuki Dohmae
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Publication number: 20060245259Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: ApplicationFiled: April 28, 2006Publication date: November 2, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae
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Publication number: 20060077712Abstract: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: ApplicationFiled: November 30, 2005Publication date: April 13, 2006Inventors: Tomoharu Tanaka, Khandker Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
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Patent number: 6990018Abstract: A non-volatile semiconductor memory device including a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: GrantFiled: April 14, 2004Date of Patent: January 24, 2006Assignees: Kabushiki Kaisha Toshiba, SanDisk CorporationInventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
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Publication number: 20040257874Abstract: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: ApplicationFiled: April 14, 2004Publication date: December 23, 2004Inventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato