Patents by Inventor Hiroyuki Enomoto

Hiroyuki Enomoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080259733
    Abstract: A technology capable of improving receiver sensitivity and improving insulation withstand voltage in an ultrasonic transducer is provided. An ultrasonic transducer comprises: a lower electrode; an insulator covering the lower electrode; a cavity portion disposed on the insulator so as to overlap with the lower electrode; and an upper electrode disposed so as to overlap with the cavity portion. In this ultrasonic transducer, an insulator is inserted between the upper and lower electrodes in a part not having the cavity portion. By this means, sum total of thickness of insulators between the upper and lower electrodes in a part not having the cavity portion is larger than sum total of thickness of insulators between the upper and lower electrodes in a part having the cavity portion.
    Type: Application
    Filed: October 4, 2007
    Publication date: October 23, 2008
    Inventors: Shuntaro Machida, Hiroyuki Enomoto
  • Patent number: 7411260
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 12, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida
  • Publication number: 20080079099
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Application
    Filed: July 6, 2007
    Publication date: April 3, 2008
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida
  • Publication number: 20080042225
    Abstract: This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.
    Type: Application
    Filed: February 5, 2007
    Publication date: February 21, 2008
    Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki
  • Publication number: 20080001239
    Abstract: The performance of a sensor in a semiconductor device can be improved. A plurality of oscillators forming an ultrasonic sensor are arranged on a main surface of a semiconductor chip. A negative-type photosensitive insulating film which protects the oscillators is deposited on an uppermost layer of the semiconductor chip. At the time of exposure for forming an opening in the photosensitive insulating film, the semiconductor chip is divided into a plurality of exposure areas and exposed, and then, the exposure areas are jointed so that the entire area is exposed. At this time, a stitching exposure area is arranged so that a center of the stitching exposure area in a width direction in the joint portion of the adjacent exposure areas is positioned at a center of a line which connects centers of oscillators located above and below the stitching exposure area.
    Type: Application
    Filed: June 25, 2007
    Publication date: January 3, 2008
    Inventors: Hiroyuki Enomoto, Katsuya Hayano, Shuntaro Machida
  • Publication number: 20080003770
    Abstract: An insulating film on a semiconductor substrate has a first titanium nitride film, an aluminum film, and a second titanium nitride film formed thereon, and an insulating film is formed so as to cover a lower electrode wiring. Then, the insulating film is dry-etched anisotropically so that the insulating film on the lower electrode wiring is removed, and a portion of the insulating film on the lower electrode wiring is left as a sidewall. A deposit deposited during the etching of the insulating film on the lower electrode wiring is removed by radical etching without using ion bombardment. The deposit contains Ti that is a metal element forming the second titanium nitride film. Subsequently, the second titanium nitride film is nitrided through ammonium plasma, and an insulating film to cover the lower electrode wiring is formed.
    Type: Application
    Filed: June 25, 2007
    Publication date: January 3, 2008
    Inventors: Hiroyuki Enomoto, Shoichi Uno, Seiko Ishihara, Takashi Yahata
  • Publication number: 20070222338
    Abstract: In an ultrasonic transducer including a gap between an upper electrode and a lower electrode on a silicon substrate, it is made possible to reduce or adjust warpage of an above-gap membrane vibrated by electrostatic actuation due to internal stress. A fourth insulating film and a fifth insulating film of films positioned above the gap which is a cavity required for transmitting and receiving ultrasonic are respectively a silicon oxide film for compression stress and a silicon nitride film for tensile stress. Therefore, compression stress and tensile stress cancel each other, so that warpage of the above-gap membrane is reduced. An amount of warpage can be adjusted by adjusting a film thickness of the fourth insulating film and a film thickness of the fifth insulating film.
    Type: Application
    Filed: January 23, 2007
    Publication date: September 27, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Takanori Aono, Tatsuya Nagata, Hiroyuki Enomoto, Shuntaro Machida
  • Publication number: 20070188442
    Abstract: A display medium includes a pair of substrates, an electrophoretic medium, and a partitioning medium. The pair of substrates is disposed in spaced-apart relation and substantially parallel to each other. The electrophoretic medium is disposed between the pair of substrates and contains charged particles. An electric field generated between the pair of substrates causes the charged particles contained in the electrophoretic medium to migrate for switching a display state. The partitioning medium has fluidity and is phase-separated from the electrophoretic medium at least at room temperature. The partitioning medium is in a phase-separated state phase-separated from the electrophoretic medium. The partitioning medium is disposed between the pair of substrates as a partition to partition the electrophoretic medium.
    Type: Application
    Filed: March 24, 2007
    Publication date: August 16, 2007
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Yasuhiro Hattori, Hiroyuki Enomoto
  • Publication number: 20070177249
    Abstract: A manufacturing apparatus for manufacturing a display medium, the manufacturing apparatus including an image data storing unit that stores image data for text or image to be displayed on the display medium; an electrode pattern generating unit that generates an electrode pattern based on the image data stored in the image data storing unit so that when the text or image is configured of a plurality of independent regions, the electrode pattern has a plurality of integrally and electrically connected electrodes corresponding to a plurality of regions; an electrode forming unit that forms the first electrode on either an electrophoretic medium integrally configured of the second substrate, the second electrode, and the electrophoretic layer or the first substrate based on the electrode pattern generated by the electrode pattern generating unit; and a bonding unit that bonds the electrophoretic medium to the first substrate after the electrode forming unit has formed the first electrode.
    Type: Application
    Filed: March 16, 2007
    Publication date: August 2, 2007
    Applicant: BROTHER KOGYO KABUSHIKIKI KAISHA
    Inventors: Yasuhiro Hattori, Hiroyuki Enomoto
  • Patent number: 7248959
    Abstract: An electronic control apparatus includes a control circuit and has a power supply holding function whereby when a power switch-off command is received by the apparatus, the supplying of power to the control circuit is continued until it has completed specific processing, during a power supply holding interval. The duration of each such interval is measured and stored in non-volatile memory, and subsequently used for detecting any power supply holding function abnormality, and for ensuring that the specific processing is actually performed, and distinguishing between an abnormality causing premature switch-off and an abnormality causing failure to terminate the supplying of power.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: July 24, 2007
    Assignee: DENSO Corporation
    Inventors: Hiroyuki Enomoto, Kokichi Shimizu, Nobuyuki Kondo
  • Publication number: 20070133376
    Abstract: For providing a read apparatus and a method of detecting deterioration of a disk, which can detect the deterioration of the disk securely at a low cost, when focus adjust and tracking adjust of an optical pick-up 3 can be acted normally within adjustable range by a servo DSP 5, the deterioration of the disk is detected based on a focus adjust value and a tracking adjust value.
    Type: Application
    Filed: March 30, 2005
    Publication date: June 14, 2007
    Inventors: Shinichiro Abe, Hiroyuki Enomoto, Kazuhiko Oogami, Kazushige Kawana, Teruo Takahashi
  • Publication number: 20070072408
    Abstract: The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched.
    Type: Application
    Filed: September 13, 2006
    Publication date: March 29, 2007
    Inventors: Hiroyuki Enomoto, Kazutami Tago, Atsushi Maekawa
  • Publication number: 20070052093
    Abstract: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.
    Type: Application
    Filed: July 20, 2006
    Publication date: March 8, 2007
    Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki, Tatsuya Nagata
  • Publication number: 20060287805
    Abstract: An electronic control apparatus includes a control circuit and has a power supply holding function whereby when a power switch-off command is received by the apparatus, the supplying of power to the control circuit is continued until it has completed specific processing, during a power supply holding interval. The duration of each such interval is measured and stored in non-volatile memory, and subsequently used for detecting any power supply holding function abnormality, and for ensuring that the specific processing is actually performed, and distinguishing between an abnormality causing premature switch-off and an abnormality causing failure to terminate the supplying of power.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 21, 2006
    Applicant: Denso Corporation
    Inventors: Hiroyuki Enomoto, Kokichi Shimizu, Nobuyuki Kondo
  • Patent number: 7141471
    Abstract: A sidewall insulating film (11) made of a silicon oxide film is formed on the sidewall of a gate electrode (7) (word line) with an aim to reduce the capacitance to the word line serving as the major component of the bit line capacitance. Also, when openings for connecting the bit lines are formed above the spaces of the gate electrodes (7) (word lines) by the dry etching of a silicon oxide film (31) above contact holes (12), a silicon nitride film (19) to be an etching stopper is provided below the silicon oxide film (31) so as to reduce the amount of the bottom surface of the opening receded below the upper surface of a cap insulating film (9).
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: November 28, 2006
    Assignee: Elpida Memory, Inc.
    Inventors: Satoru Yamada, Hiroyuki Enomoto, Nobuya Saito, Tsuyoshi Kawagoe, Hisaomi Yamashita
  • Publication number: 20060008258
    Abstract: An information reproducing device includes a setting unit that sets priority for displaying appended data appended to compressed data in a compressed data file, such as an MP3 file. The appended data is appended at various positions to the compressed data. A reading unit reads a compressed data file, an extracting unit extracts appended data from the compressed data file based on the priority set, and a display unit displays the extracted appended data. A reproducing unit reproduces the compressed data.
    Type: Application
    Filed: May 27, 2005
    Publication date: January 12, 2006
    Inventors: Kazushige Kawana, Akihiro Hashimoto, Kazuhiko Oogami, Hideyasu Iwano, Hiroyuki Enomoto, Shinichiro Abe, Hiroyuki Akama, Masakazu Takahashi
  • Publication number: 20050026424
    Abstract: The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched.
    Type: Application
    Filed: August 24, 2004
    Publication date: February 3, 2005
    Inventors: Hiroyuki Enomoto, Kazutami Tago, Atsushi Maekawa
  • Patent number: 6849885
    Abstract: An amount of a semiconductor substrate cut due to etching in the bottom of a contact hole formed by the SAC technique is reduced. Silicon oxide films are dry etched under the conditions of increasing the etching selective ratio of the silicon oxide films to an insulating film. Then, the conditions are changed to those increasing the etching selective ratio of the insulating film to the silicon oxide films and the insulating film is etched by a predetermined amount.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: February 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Enomoto, Hiroyuki Maruyama, Makoto Yoshida
  • Patent number: 6806195
    Abstract: To provide a manufacturing method of the semiconductor IC device having fine-structure connecting holes or trenches with high dimensional precision. There is the following step of the operation: a hook-shaped hard mask made of polysilicon film 18 and polysilicon film 20a is formed on the surface of silica film 17 for forming connecting holes 21 accommodating plugs that perform an electrical connection with the lower portion of the lower electrode of the capacitor in the COB-type memory cells, with the hook-shaped hard mask being used as an etching mask in selective etching so as to form connecting holes 21 on silica film 17 and silica film 15 below it.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: October 19, 2004
    Assignees: Texas Instruments Incorporated, Hitachi Ltd.
    Inventors: Hiroyuki Enomoto, Kazuo Yamazaki, Masayuki Yasuda
  • Patent number: 6791137
    Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Yamada, Kiyonori Oyu, Takafumi Tokunaga, Hiroyuki Enomoto, Toshihiro Sekiguchi