Abstract: A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.

Abstract: A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.

Abstract: A circuit includes a register which stores therein a semaphore address, and further includes a semaphore control circuit which asserts a control signal in response to a read access by a processor directed to the semaphore address, and negates the control signal in response to a write access by the processor directed to the semaphore address.

Abstract: A circuit includes a register which stores therein a semaphore address, and further includes a semaphore control circuit which asserts a control signal in response to a read access by a processor directed to the semaphore address, and negates the control signal in response to a write access by the processor directed to the semaphore address.

Abstract: A processor 11A comprises a processor core 11 connected to an internal bus 14, an interface circuit 12 connected between the internal bus 14 and an external bus 22, and an interface circuit 13 connected between the internal bus 14 and an external bus 24. To simplify bus arbitration, the interface circuit 12 holds an address on the internal bus 14 in an first address buffer register 121 in response to an internal address strobe signal *ASi, judges based on the address value whether or not an access request is performed, outputs a bus request signal *PREQ, outputs the content of the first address register 121 onto the external bus 22 after getting a bus ownership, thereafter provides the data on the external bus 22 to the internal bus 14, and provides an internal ready signal *RDYi to the processor core 11. The processor may comprise a between-interface control circuit to enable to connect between the external circuits 22 and 24 in common.

Abstract: Disclosed are a semiconductor device of which a block having a plurality of portions that operate based on a plurality of clocks can be designed and inspected easily, and a method of designing the semiconductor device. First and second clocks whose frequencies are mutually different are used to generate an enabling signal that is validated only during a short period including a transition edge of the second clock. The enabling signal and first clock are supplied to the second portion. The second portion synthesizes the enabling signal and first clock to substantially generate the second clock. Thus, the second portion is regarded as a portion that operates synchronously with the first clock.

Abstract: A method and apparatus for controlling transfer of data in which a plurality of burst transfer operations starting from an arbitrary byte as a start address are performed consecutively without a high-speed adder provided in the conventional data transfer apparatus performing burst transfer. Data is transferred between memories by a plurality of consecutive burst transfer operations performed on data stored in consecutive addresses. Each of the burst transfer operations is performed on the data stored in a respective one of memory cell areas each of which corresponds to a unit of burst transfer. A first address representing an address of one of the memory cell areas storing data to be transferred is calculated. The first address is a part of a start address of a second or later burst transfer operation. A second address representing an address of one of memory cells provided in the one of the memory cell areas is calculated separately. The data transfer operation is started from the one of the memory cells.

Abstract: A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses.

Abstract: A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.

Abstract: A memory accessing device is connected to a central processing unit and a memory unit via a common bus. The memory accessing device accesses the memory unit independently of the central processing unit. The device includes an address generating unit for generating an address, an address control unit for outputting the generated address to the bus, and a control unit for controlling the address control unit to suspend or terminate memory access controlled in an address pipeline mode when the memory accessing device internally or externally issues a request for the suspension or the termination of the memory access controlled in the address pipeline mode. The control unit terminates or suspends the memory access when it receives a request internally or externally of the memory accessing device for the suspension or the termination of the memory access.

Abstract: A grouping device comprises a register table and a grouping unit the register table having m registers corresponding to m groups, each register including an n-bits data storing portion corresponding to the n input signals, for registering relationships between the n input signals and the m groups, the grouping unit receiving grouping signals output from the register table and the n input signals, for selecting one group from the m groups for each input signal and grouping each input signal into the selected group in accordance with the register table. Therefore, the register access time is shortened and the confirmation of the contents of the register by the CPU is made easier.

Abstract: An interrupt processing method and an interrupt processing apparatus provides an end indicative information storing unit for storing an end indicative information of a daisy chain for at least one of a plurality peripheral units, the peripheral unit receiving the indicative information when the peripheral unit receives an acknowledge signal but does not output a request signal, and the peripheral unit outputs a specific chain end state signal to the central processing unit, so that the central processing unit is returned from a response waiting state. Therefore, when an error request signal is produced by noise, etc., delay at a central processing unit is reduced. Further, the daisy chain connection is cut at an optional portion and a request signal from an irrevelant peripheral unit is ignored, so that the efficiency of the processing is improved.

Abstract: A register circuit comprises a plurality of registers commonly receiving a data signal and selection signals respectively, each of the registers including a first input terminal for receiving the data signal; a second input terminal for receiving a corresponding one of the selection signals; an output terminal for outputting a stored data signal; a storing unit, connected to the output terminal, for storing the data signal; and a control unit, connected to the storing unit, the first input terminal, the second input terminal, and the output terminal, for transferring the data signal to the storing unit when the selection signal is effective and resetting the storing unit when the data signal is already stored in the storing unit and the selection signal is not effective.