Abstract: A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.

Abstract: A scan separator in a large scale integration device is made more extensive to suppress an increase in the circuit scale of the entire device. In one embodiment, a scan separator is provided for every two signal lines interconnecting two combinatorial circuit blocks. Each scan separator includes a selector and a flip flop for constituting a scan path. Another selector is provided for selecting one of the two signal lines. As an input selector signal for the selector that selects one of the two signal lines, data for switching controlling are used, which are transferred from a test input terminal over the scan path and latched by the flip flop. The data for switching controlling are initially transferred over the scan path to each flip flop. The selector that selects one of the two signal lines is switched in accordance with the switching controlling data stored in the flip flop. The switching controlling data may be interchanged to select the either of the two signal lines.

Abstract: A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.

Abstract: A scan separator in a large scale integration device is made intensive to suppress the circuit scale of the entire device from increasing. A scan separator is provided for every two signal lines interconnecting two combinatorial circuit blocks. Each scan separator includes one selector, a flip flop for constituting a scan path, and another selector for selecting one of the two signal lines. As an input selector signal for the other selector, data for switching controlling are used, which are transferred from a test input terminal over the scan path and latched by the flip flop. The data for switching controlling are initially transferred over the scan path to each flip flop. The other selector is switched in accordance with the switching controlling data stored in the flip flop to select one of the two signal lines. The switching controlling data may be interchanged to select the other signal line.

Abstract: The semiconductor integrated circuit capable of reducing the length of time required for clock switching is provided. The semiconductor integrated circuit includes a clock generation control circuit which is provided with a register capable of writing and reading specific data, and generates a frequency divided clock by inputting a reference clock with the timing of a clock frequency division setting signal. A clock control circuit constituting this semiconductor integrated circuit comprises a status shift circuit that controls clock frequency division/switching, a switching timing generation circuit that measures the timing with which a clock switch is made and a selection switching circuit that makes a switch between the reference clock and the frequency divided clock.

Abstract: The semiconductor integrated circuit capable of reducing the length of time required for clock switching is provided. The semiconductor integrated circuit includes a clock generation control circuit which is provided with a register capable of writing and reading specific data, and generates a frequency divided clock by inputting a reference clock with the timing of a clock frequency division setting signal. A clock control circuit 8 constituting this semiconductor integrated circuit comprises a status shift circuit 236 that controls clock frequency division/switching, a switching timing generation circuit that measures the timing with which a clock switch is made and a selection switching circuit that makes a switch between the reference clock and the frequency divided clock.