Abstract: The present invention provides a solid-state imaging device which is capable of high-speed and high-quality pixel mixture. The solid-state imaging device includes: a plurality of pixels; a row selecting circuit; a plurality of column signal lines each of which is provided to a corresponding one of columns of pixels, is connected to pixels of the corresponding column, and transfers the signals outputted from the connected pixels; a pixel current source which (i) is provided to a corresponding one of the column signal lines, (ii) is connected to the corresponding column signal line, and (iii) supplies to the connected column signal line a current when the signal is outputted from the selected pixel to the connected column signal line; and a control unit which changes the number of rows of pixels being simultaneously selected by the row selecting circuit, and values of the current supplied by the pixel current source.

Abstract: Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is connected between the bus lines and a power source. A state detector detects a frozen state on the basis of the states of the SCL line and SDA line and outputs a freeze detection signal, and it detects a freeze released state so as to output a freeze-release detection signal. A pulse generator supplies a pulse signal corresponding to a clock signal to the SCL line in accordance with the freeze-release detection signal. A reset signal generator sends a reset signal to the multiple master devices in accordance with the freeze-release detection signal. The multiple master devices return to the normal communication state in accordance with the supply of the reset signal. It is possible to restore the system even when the slave device returns an acknowledge signal for an incorrect bit and the IIC bus communication freezes.

Abstract: The present invention provides a solid-state imaging device which is capable of high-speed and high-quality pixel mixture. The solid-state imaging device includes: a plurality of pixels; a row selecting circuit; a plurality of column signal lines each of which is provided to a corresponding one of columns of pixels, is connected to pixels of the corresponding column, and transfers the signals outputted from the connected pixels; a pixel current source which (i) is provided to a corresponding one of the column signal lines, (ii) is connected to the corresponding column signal line, and (iii) supplies to the connected column signal line a current when the signal is outputted from the selected pixel to the connected column signal line; and a control unit which changes the number of rows of pixels being simultaneously selected by the row selecting circuit, and values of the current supplied by the pixel current source.

Abstract: Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is connected between the bus lines and a power source. A state detector detects a frozen state on the basis of the states of the SCL line and SDA line and outputs a freeze detection signal, and it detects a freeze released state so as to output a freeze-release detection signal. A pulse generator supplies a pulse signal corresponding to a clock signal to the SCL line in accordance with the freeze-release detection signal. A reset signal generator sends a reset signal to the multiple master devices in accordance with the freeze-release detection signal. The multiple master devices return to the normal communication state in accordance with the supply of the reset signal. It is possible to restore the system even when the slave device returns an acknowledge signal for an incorrect bit and the IIC bus communication freezes.

Abstract: Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is connected between the bus lines and a power source. A state detector detects a frozen state on the basis of the states of the SCL line and SDA line and outputs a freeze detection signal, and it detects a freeze released state so as to output a freeze-release detection signal. A pulse generator supplies a pulse signal corresponding to a clock signal to the SCL line in accordance with the freeze-release detection signal. A reset signal generator sends a reset signal to the multiple master devices in accordance with the freeze-release detection signal. The multiple master devices return to the normal communication state in accordance with the supply of the reset signal. It is possible to restore the system even when the slave device returns an acknowledge signal for an incorrect bit and the IIC bus communication freezes.

Abstract: Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is connected between the bus lines and a power source. A state detector detects a frozen state on the basis of the states of the SCL line and SDA line and outputs a freeze detection signal, and it detects a freeze released state so as to output a freeze-release detection signal. A pulse generator supplies a pulse signal corresponding to a clock signal to the SCL line in accordance with the freeze-release detection signal. A reset signal generator sends a reset signal to the multiple master devices in accordance with the freeze-release detection signal. The multiple master devices return to the normal communication state in accordance with the supply of the reset signal. It is possible to restore the system even when the slave device returns an acknowledge signal for an incorrect bit and the IIC bus communication freezes.

Abstract: Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is connected between the bus lines and a power source. A state detector detects a frozen state on the basis of the states of the SCL line and SDA line and outputs a freeze detection signal, and it detects a freeze released state so as to output a freeze-release detection signal. A pulse generator supplies a pulse signal corresponding to a clock signal to the SCL line in accordance with the freeze-release detection signal. A reset signal generator sends a reset signal to the multiple master devices in accordance with the freeze-release detection signal. The multiple master devices return to the normal communication state in accordance with the supply of the reset signal. It is possible to restore the system even when the slave device returns an acknowledge signal for an incorrect bit and the IIC bus communication freezes.

Abstract: Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is connected between the bus lines and a power source. A state detector detects a frozen state on the basis of the states of the SCL line and SDA line and outputs a freeze detection signal, and it detects a freeze released state so as to output a freeze-release detection signal. A pulse generator supplies a pulse signal corresponding to a clock signal to the SCL line in accordance with the freeze-release detection signal. A reset signal generator sends a reset signal to the multiple master devices in accordance with the freeze-release detection signal. The multiple master devices return to the normal communication state in accordance with the supply of the reset signal. It is possible to restore the system even when the slave device returns an acknowledge signal for an incorrect bit and the IIC bus communication freezes.

Abstract: A signal detection device is composed of a SAP detecting circuit that outputs a voltage corresponding to the level of a SAP signal; a noise detecting circuit that outputs a voltage corresponding to the level of a noise component; a SAP signal detection comparator that is capable of changing, if the level of a SIF signal is reduced, a reference bias according to that level and that determines whether there is a SAP signal based on the reference bias; a noise detection comparator that determines whether there is a noise component; and a SAP detection signal generating circuit that uniformly outputs, if the noise detection comparator determines that there is noise, a signal indicating that there is no SAP signal.