Patents by Inventor Hiroyuki Hiramoto

Hiroyuki Hiramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090237890
    Abstract: A semiconductor device includes: a semiconductor element (106) having a surface on a positive electrode side and a surface on a negative electrode side; multiple conductors (13 to 15) bonded respectively to the surface on the positive electrode side and to the surface on the negative electrode side of the semiconductor element; a heat sink plate (11) disposed as intersecting a junction interface between the semiconductor element and each of the multiple conductors and configured to discharge heat of the semiconductor element; and an insulator (12) bonding the heat sink plate to the multiple conductors. The insulator includes a heat conductive insulator (16) disposed inside a portion facing all of the multiple conductors and a flexible insulator (17) disposed at a portion other than the heat conductive insulator.
    Type: Application
    Filed: February 1, 2007
    Publication date: September 24, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroki Sekiya, Toshiharu Oobu, Ryuichi Morikawa, Gou Ninomiya, Hiroyuki Hiramoto
  • Patent number: 7263766
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: September 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Publication number: 20030168729
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Application
    Filed: January 27, 2003
    Publication date: September 11, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Patent number: 6605868
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: August 12, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Patent number: 6597063
    Abstract: A package for a semiconductor power device which comprises: a conductive bottom plate as a heat sink; an insulating substrate mounted on the bottom plate; a copper film formed on the insulating substrate to expose a peripheral region of the insulating substrate; semiconductor chips disposed on the copper film; a container arranged on the bottom plate, surrounding the insulating substrate; an external terminal supported through the container and connected electrically with the semiconductor chips; and a silicone gel filled within the container, wherein a solidified insulating material is disposed on an outer edge region of the copper film and the peripheral region of the insulating substrate. Thus, reducing an electric field across the interface and making it difficult to cause a creeping discharge. A notch is formed in the bottom plate, and the notch is filled with a high heat conductive resin. The notch is located outwardly apart from a region where the semiconductor chips are mounted.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: July 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Shimizu, Hiroyuki Hiramoto, Hiroki Sekiya, Kenji Kigima
  • Publication number: 20020066953
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Application
    Filed: December 9, 1999
    Publication date: June 6, 2002
    Inventors: YUTAKA ISHIWATA, KOSOKU NAGATA, TOSHIO SHIMIZU, HIROYUKI HIRAMOTO, YASUHIKO TANIGUCHI, KOUJI ARAKI, HIROSHI FUKUYOSHI, HIROSHI KOMORITA
  • Patent number: 6201696
    Abstract: A package for a semiconductor power device which comprises: a conductive bottom plate as a heat sink; an insulating substrate mounted on the bottom plate; a copper film formed on the insulating substrate to expose a peripheral region of the insulating substrate; semiconductor chips disposed on the copper film; a container arranged on the bottom plate, surrounding the insulating substrate; an external terminal supported through the container and connected electrically with the semiconductor chips; and a silicone gel filled within the container, wherein a solidified insulating material is disposed on an outer edge region of the copper film and the peripheral region of the insulating substrate. Thus, reducing an electric field across the interface and making it difficult to cause a creeping discharge. A notch is formed in the bottom plate, and the notch is filled with a high heat conductive resin. The notch is located outwardly apart from a region where the semiconductor chips are mounted.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: March 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Shimizu, Hiroyuki Hiramoto, Hiroki Sekiya, Kenji Kigima