Patents by Inventor Hiroyuki Iki

Hiroyuki Iki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electromagnetic field analysis method based on FDTD method, medium representation method in electromagnetic field analysis, simulation device, and storage medium
    Patent number: 6772076
    Abstract: A conductor is represented by a line. A plane on which the conductor crosses a plurality of sides in the planes forming a cell is divided by the conductor. In the planes obtained by the division, a plane containing the position in which the magnetic field intensity is obtained is processed as one plane as is, and a plane not containing the position is added to an adjacent plane. On the side crossing the conductor, the two values of the field intensity are defined. That is, the magnetic field intensity is obtained through the integral loop containing the conductor for each of the divided plane processed as one plane, and the plane to which the divided plane not processed as one plane is added.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: August 3, 2004
    Assignees: FFC Limited
    Inventors: Kazuo Yamamoto, Hiroyuki Iki
  • Electromagnetic field analysis method based on FDTD method, medium representation method in electromagnetic field analysis, simulation device, and storage medium
    Publication number: 20030204343
    Abstract: A conductor is represented by a line. A plane on which the conductor crosses a plurality of sides in the planes forming a cell is divided by the conductor. In the planes obtained by the division, a plane containing the position in which the magnetic field intensity is obtained is processed as one plane as is, and a plane not containing the position is added to an adjacent plane. On the side crossing the conductor, the two values of the field intensity are defined. That is, the magnetic field intensity is obtained through the integral loop containing the conductor for each of the divided plane processed as one plane, and the plane to which the divided plane not processed as one plane is added.
    Type: Application
    Filed: May 29, 2002
    Publication date: October 30, 2003
    Applicant: FFC LIMITED & KAZUO YAMAMOTO
    Inventors: Kazuo Yamamoto, Hiroyuki Iki