Abstract: A replay signal, obtained on reproducing a recording medium, on which has been recorded a digital signal, is supplied to an input terminal (1), and quantized by an A/D converter (8). The so quantized signal is processed by an integrator (20), formed by a first order IIR filter, so as to be adjusted in gain by an amplifier (21). The quantized replay signal is also processed by a differentiator formed by a combination of a first order FIR filter (22) and a first order IIR filter (23) so as to be then adjusted in gain by an amplifier (24). The resulting signal is then supplied to an adder (25) where it is subtracted from an output signal of the amplifier (21). In this manner, the differentiation/integration equalizer, formed by an analog circuit, is constructed by a digital circuit of a simplified configuration without raising the number of orders of the filters. The replay signal is processed by differentiation/integration such as to satisfy the equalization standard.

Abstract: A signal processing apparatus adapted for correcting non-linear distortion of a reproduction signal includes a secondary adaptive equalizing filter connected in parallel with a primary adaptive equalizing filter to correct non-linear distortion in an analog equalized signal. Filter outputs of the primary adaptive equalizing filter and the secondary adaptive equalizing filter are added at an adder, and the added output thus obtained is delivered to a phase interpolation filter as an equalized output. The phase interpolation filter performs interpolation of phase on the basis of a filter output of the primary adaptive equalizing filter and a filter output of the secondary adaptive equalizing filter. A filter output of the phase interpolation filter is delivered to an Information Technology research-phase-locked loop circuit.

Abstract: A replay signal, obtained on reproducing a recording medium, on which has been recorded a digital signal, is supplied to an input terminal (1), and quantized by an A/D converter (8). The so quantized signal is processed by an integrator (20), formed by a first order IIR filter, so as to be adjusted in gain by an amplifier (21). The quantized replay signal is also processed by a differentiator formed by a combination of a first order FIR filter (22) and a first order IIR filter (23) so as to be then adjusted in gain by an amplifier (24). The resulting signal is then supplied to an adder (25) where it is subtracted from an output signal of the amplifier (21). In this manner, the differentiation/integration equalizer, formed by an analog circuit, is constructed by a digital circuit of a simplified configuration without raising the number of orders of the filters. The replay signal is processed by differentiation/integration such as to satisfy the equalization standard.

Abstract: A method and apparatus for Viterbi detection to detect a code sequence containing a sync word, from an output sequence on a transmission path, by using a trellis detection that has a time-variant structure. The apparatus comprising a base counter for measuring time during the trellis detection, a comparator for comparing the time when the sync word is detected and outputting a coincidence/non-coincidence signal, and a selector for selecting either an output of an ACS (Add Compare Select) circuit or a predetermined initial metric value. The likelihood of a state in which the sync word starts or ends in the trellis detection is initialized only if the time the sync word is detected does not coincide with a time extrapolated before the sync word is detected.

Abstract: In order to detect a code sequence containing a sync word, from an output sequence on a transmission path, by using a detection trellis that has a time-variant structure, a base counter 48 measures time in the detection trellis. A comparator 49 compares the time when the sync word is detected, with the time indicated by the base counter 48, and outputs a coincidence/non-coincidence signal. A selector 46 selects either an output of an ordinary ACS (Add Compare Select) circuit or a predetermined initial metric value, in accordance with the output of the comparator 49. More precisely, the selector 46 selects the output of the ordinary ACS circuit when the output of the comparator 49 indicates coincidence, and selects a prescribed initial metric value when the output of the comparator 49 indicates non-coincidence.

Abstract: In encoding method and device for encoding m-bit data to an n-bit code, the n-bit code is generated according to a finite state transition diagram representing the restriction of ADS and RDS received by a code sequence; two states contained in a state assembly set as start points of the n-bit code in the finite state transition diagram exist at symmetrical positions with respect to the center point of the finite state transition diagram, at symmetrical positions with respect to the ADS axis passing through the center point of the finite state transition diagram or at the symmetrical positions with respect to the RDS axis passing the center point of the finite state transition diagram; the m-bit data are encoded to an n-bit code word having as a start point a predetermined state contained in a state assembly set as start points of the code; and an n-bit code word having as a start point another state contained in a state assembly set as start points by the code is obtained by further converting the encoded cod

Abstract: The subtracter performs subtraction processing between a pointer outputted from the pointer register and code words candidate outputted from the code word count storing circuit, and in accordance with whether the result is negative or positive, determines the code words of input data words. Code word candidates stored in the code word count storing circuit are created according to a finite-state transition diagram stored in the state transition storing circuit. An encoder and a decoder are thus made compact and faster.

Abstract: The present invention relates to an apparatus for azimuth-recording data on a magnetic recording medium. Heads (13a) and (13b) having azimuth angles different from each other are used and data are recorded on and reproduced from a plurality of adjacent tilted recording tracks on a magnetic tape T. A recording-system encoder (23) converts data to a code sequence in which null points of frequency spectrums are respectively provided at null points of waveform equalization characteristics of partial responses such as PR1, PR4, etc. For example, record-coding using a 8/10MSN code is performed. A reproduction-system equalizing circuit (28) performs waveform equalization based on the partial responses. Further, a data detector (29) detects the data by a Viterbi coding method for executing state transition during which the characteristic of the code sequence is adopted.

Abstract: Partial response (1, 1) is applied to a partitioned MSN (partitioned-matched spectral null) code. A branch metric (BM) obtained in a calculation block is directly supplied to a selector, and it is also supplied to the selector via an adder. The adder adds a predetermined value to the branch metric in such a manner as to decrease the degree of likelihood associated with a state transition corresponding to the branch metric. A determination block detects an invalid state transition in a detection trellis, which cannot be generated by the partitioned MSN code, on the basis of the number of 1s or 0s included in the partitioned MSN code. The selector selects either the branch metric added with the predetermined value or the branch metric added with no predetermined value depending on the detection result of the determination block. A path metric is calculated using the selected branch metric added with the predetermined value or added with no predetermined value.

Abstract: In a data decoding apparatus of this invention, level of a reproduction RF signal 7a at the time of the binary level judgment of channel bit is temporarily stored into a RF signal level memory section 20. The portions which do not satisfy the conditions of the minimum run length and the maximum run length of the same symbols within the channel bit data train are respectively detected by a (d'-1) detecting section 16 and a (k'+1) detecting section 17. This data decoding apparatus comprises correction bit position detecting sections 18, 19 for outputting correction bit position designation signals on the basis of level of the RF signal at the time of the binary level judgment stored in the RF signal level memory section 20, and a bit data inversion correcting section 15 for inverting logic level of data at bit position designated on the basis of the correction bit position designation signals 18a, 18b, 19a, 19b.

Abstract: If there is any portion in channel bit data obtained on converting a signal read out from a recording medium into a bi-level signal which fails to satisfy a condition concerning a minimum run length or a maximum run length of the same symbol, the channel bit data is corrected to improve the bit error rate to secure a skew margin. To this end, channel bit data not satisfying a minimum run length d' of the same symbol is detected by a (d'-1) detector 4 using n-tupled clocks obtained on n-tupling channel clocks of playback data by a bit clock generator 2, where n is an integer not less than 2. A correction position of the channel bit data having the run length of the same symbol equal to (d'-1) is designated by a correction bit position designating unit 5. A data correction unit 6 then corrects the channel bit data so that the minimum run length of the same symbol will be equal to d'.

Abstract: A Viterbi decoding method and decoder are provided for achieving a faster operation than the prior art. The Viterbi decoding method and decoder are arranged to determine the most approximate path on two-state state metrics and decode the data on the most approximate path. The Viterbi decoder includes registers 2 and 3 for reading two pieces of sample data, an adder 14 for adding two pieces of sample data read by the registers 2 and 3, and an arrangement located after the adder 14 for determining a path of each state transition by comparing the added result with a given identification of -1, 0 or 1.

Abstract: In data reproducing device, a reproducing signal is detected from a magnetic recording medium in which data is recorded, and an equalizer equalizes the reproducing signal. A sampling circuit samples the reproducing signal from the equalizer, and a filter having a characteristic of linearly delaying a phase of the reproducing signal in a frequency range not higher than a predetermined frequency performs filtering of the resulting sampled value. Thus, phase compensation in a low frequency range of the reproducing signal can be performed satisfactorily in comparison with the conventional device.

Abstract: 5*3 states are arranged on a plane composed of the horizontal axis and vertical axis, 2-bit data of 01, 10, 00, and 11 are assigned to the state transitions in the up, down, right, and left-directions respectively in the 3*5 states. A 20-bit code is generated by 10 times the state transitions. 2.sup.16 20-bit codes are prepared and these codes have a one-to-one correspondence to 16-bit data (2.sup.16). The end point of the previous state transition is the starting point of the next state transition, and 16-bit data are converted successively to 20-bit codes while the state transitions occur continuously. In the manner as described above, the conversion efficiency in PR (1, 1) is improved.

Abstract: A synchronization signal detector for detecting synchronization signals or frame synchronization signals recorded on a recording medium includes a binary-valued signal detector for translating RF signals into binary-valued signals, an edge detection circuit for extracting edge portions of the binary-valued signals, a counter for counting the number of clocks generated by an external source between the edge portions, a number of latch circuits for holding successive clock count values between the edge portions and for successively shifting the clock values held by them, value coincidence circuits for comparing the numbers of clocks between transitions of the synchronization patterns and the clock count values held by the counter and the latch circuits and for outputting a signal indicating a coincidence in case of complete coincidence between the numbers of clocks and the clock count values and an AND circuit for taking a logical sum of the outputs of the value coincidence circuits and the edge detector for pr

Abstract: Carrying out DSV control with a PR(1, 1) while making free distance larger and path memory length shorter. "3.times.3" states are arranged in a plane defined by a horizontal axis and a vertical axis, with a code 11 being allotted to correspond to rightward transitions along the horizontal axis and a code 00 being allotted to correspond to leftward transitions. A code 01 is allotted to upward transitions along the vertical axis and a code 10 is allotted to correspond to downward transitions. Codes obtained in the case of transitions from a start point taken as one of the states 1, 3, 5 or 7, to the states 1, 3, 5 or 7 taken as end points through the other five states are used as codes after conversion. For example, the codes 01, 01, 11, 00, 10 and 10 are obtained from a transition through state 1, state 4, state 7, state 8, state 7, state 4 and state 1.

Abstract: A synchronization detector includes a NRZI circuit for extracting edge portions of RF signals detected as binary-valued signals to form a pulse train, a counter for counting the number of channel clocks in the distance between transitions represented by the edge portions, a latch circuit operated responsive to pulses from the NRZI circuit for holding a number of previously counted channel clocks immediately preceding a current count of channel clocks, and AND gates and an OR gate for detecting synchronization signals when the combination of the channel clocks from the counter and the latch circuit is the combination of the maximum distance between transitions Tmax and Tmax-kT (k=1 or 2) of a (d, k; m, n; r) modulation code. Synchronization signals may be detected promptly even if the frame structure is increased in size to enable restoration of synchronization to be expedited when frame structure synchronization is not in order. A demodulator utilizing the synchronization signal detector is also disclosed.

Abstract: A modulating method, a modulating device and a demodulating device, in which it is possible to improve the digital sum value (DSV) of the coded information, modulated for transmission or recording on the recording medium, are disclosed. An encoding circuit 11 translates a sequence of input data into a sequence of coded data suitable for transmission. A pattern generating circuit 12 generates a pattern of a pre-set length at a pre-set interval inversely proportionate to the low-range cut-off frequency of the modulated coded data. A pattern inserting circuit 13 inserts the patterns into the sequence of coded data A at the pre-set interval. A modulating circuit 14 NRZI modulates the pattern-interlaced sequence of the coded data B and outputs the resulting sequence. A timing control circuit 15 controls the pattern inserting circuit 13 an so forth.

Abstract: In a data modulation method, m-bit data is modulated to n-bit data (n.gtoreq.m) having fewer direct current and low frequency components. A dispersion of the digital sum variation of code weights can be reduced, a direct current component is reduced and an error rate can be further reduced by selecting a plurality of modulation tables constituting the combination of one or more sub-groups of modulation data obtained by dividing a group of modulation data by a code weight having the same value based on the digital sum variation of the code weights accumulated until a time at which m-bit data is converted to n-bit code and converting next m-bit data continuously to present m-bit data to n-bit code by using the modulation tables.

Abstract: A method of modulating digital data to a variable-length code having parameters d, k, m, n, and r for recording information on and reproducing the same from an optical disc. The optimal range of a minimum run length d corresponding to the minimum number of successive same symbols is determined by a procedure which includes a first step to determine the minimum S/N required for obtaining a desired error rate from the relationship between a bit error rate and the S/N when d=0; a second step to obtain the relationship between a change of the numerical value d and that of the S/N by calculating, on the basis of the required minimum S/N obtained at the first step, the S/N loss caused due to the change of the numerical value d; and a third step to determine, from the relationship between the numerical value d and the S/N, the range of the value d corresponding to the S/N of the transmission characteristic dependent on an optical system and an optical disc.