Patents by Inventor Hiroyuki IRIFUNE
Hiroyuki IRIFUNE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527661Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a first active region; and a third electrode. The first semiconductor layer is located between the first electrode and the second electrode. The second semiconductor layer is located above the first semiconductor layer. The first active region is next to the second semiconductor layer in a second direction. The first active region includes a first upper portion and a first upper portion. An average value of a width in the second direction of the first lower portion is greater than an average value of a width in the second direction of the first upper portion. The third semiconductor layer is electrically connected with the second electrode.Type: GrantFiled: July 15, 2021Date of Patent: December 13, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Hiroyuki Irifune, Hiroshi Kono, Makoto Mizukami, Shuji Kamata
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Publication number: 20220093805Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a first active region; and a third electrode. The first semiconductor layer is located between the first electrode and the second electrode. The second semiconductor layer is located above the first semiconductor layer. The first active region is next to the second semiconductor layer in a second direction. The first active region includes a first upper portion and a first upper portion. An average value of a width in the second direction of the first lower portion is greater than an average value of a width in the second direction of the first upper portion. The third semiconductor layer is electrically connected with the second electrode.Type: ApplicationFiled: July 15, 2021Publication date: March 24, 2022Inventors: Hiroyuki IRIFUNE, Hiroshi KONO, Makoto MIZUKAMI, Shuji KAMATA
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Patent number: 9136324Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.Type: GrantFiled: December 23, 2013Date of Patent: September 15, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Kimura, Yasuto Sumi, Hiroshi Ohta, Hiroyuki Irifune
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Patent number: 8872261Abstract: A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third diffusion layers are the same.Type: GrantFiled: September 7, 2012Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Irifune, Wataru Saito, Yasuto Sumi, Kiyoshi Kimura, Hiroshi Ohta, Junji Suzuki
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Patent number: 8860144Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.Type: GrantFiled: June 14, 2013Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito, Syotaro Ono
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Publication number: 20140117445Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.Type: ApplicationFiled: December 23, 2013Publication date: May 1, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiyoshi KIMURA, Yasuto SUMI, Hiroshi OHTA, Hiroyuki IRIFUNE
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Patent number: 8680606Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode.Type: GrantFiled: March 19, 2012Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune
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Patent number: 8643056Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.Type: GrantFiled: September 9, 2011Date of Patent: February 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kiyoshi Kimura, Yasuto Sumi, Hiroshi Ohta, Hiroyuki Irifune
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Publication number: 20130277763Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Hiroshi OHTA, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito, Syotaro Ono
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Patent number: 8487374Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.Type: GrantFiled: September 16, 2011Date of Patent: July 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito, Syotaro Ono
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Publication number: 20130093003Abstract: A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same.Type: ApplicationFiled: September 7, 2012Publication date: April 18, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki IRIFUNE, Wataru SAITO, Yasuto SUMI, Kiyoshi KIMURA, Hiroshi OHTA, Junji SUZUKI
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Publication number: 20130069158Abstract: A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.Type: ApplicationFiled: March 20, 2012Publication date: March 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi OHTA, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito
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Publication number: 20120241823Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode.Type: ApplicationFiled: March 19, 2012Publication date: September 27, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: HIROSHI OHTA, YASUTO SUMI, KIYOSHI KIMURA, JUNJI SUZUKI, HIROYUKI IRIFUNE
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Publication number: 20120074491Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.Type: ApplicationFiled: September 16, 2011Publication date: March 29, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi OHTA, Yasuto SUMI, Kiyoshi KIMURA, Junji SUZUKI, Hiroyuki IRIFUNE, Wataru SAITO, Syotaro ONO
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Publication number: 20120061721Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers.Type: ApplicationFiled: September 9, 2011Publication date: March 15, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kiyoshi KIMURA, Yasuto SUMI, Hiroshi OHTA, Hiroyuki IRIFUNE
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Publication number: 20110291181Abstract: According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately.Type: ApplicationFiled: May 31, 2011Publication date: December 1, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki IRIFUNE, Yasuto Sumi, Kiyoshi Kimura, Hiroshi Ohta