Patents by Inventor Hiroyuki Iwaki

Hiroyuki Iwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11029881
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 8, 2021
    Assignee: SONY CORPORATION
    Inventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
  • Publication number: 20210131977
    Abstract: Various embodiments of systems and methods for calibrating wafer inspection system modules are disclosed herein. More specifically, the present disclosure provides various embodiments of systems and methods to calibrate the multiple spectral band values obtained from a substrate by a camera system included within a WIS module. In one embodiment, multiple spectral band values are red, green, and blue (RGB) values. As described in more detail below, the calibration methods disclosed herein may use a test wafer having a predetermined pattern of thickness changes or color changes to generate multiple spectral band offset values. The multiple spectral band offset values can be applied to the multiple spectral band values obtained from the substrate to generate calibrated RGB values, which compensate for spectral responsivity differences between camera systems included within a plurality of WIS modules.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 6, 2021
    Inventors: Michael Carcasi, Hiroyuki Iwaki, Toyohisa Tsuruda, Masahide Tadokoro
  • Publication number: 20210134637
    Abstract: Camera images may be utilized to detect substrate edges and provide information regarding the centering of the substrate within the fluid dispense system. Camera images may also be utilized to monitoring the location of a cup within the fluid dispense system. The signal processing techniques utilized may include data smoothing, analyzing only certain wavelengths of reflected energy, transforming the data (in one embodiment utilizing a Fourier transform), and/or analyzing a sub-set of the collected pixels of data. The camera image data collected herein may be combined with a wide variety of other data so as to better monitor, characterize and/or control a substrate processing process flow.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 6, 2021
    Inventors: Michael Carcasi, Joshua Hooge, Mark Somervell, Hiroyuki Iwaki, Masahide Tadokoro, Masashi Enomoto, Joel Estrella, Yuichiro Kunugimoto
  • Publication number: 20210129166
    Abstract: In a liquid dispense system, camera images may be utilized to identify puddle edges of a liquid dispensed on a substrate. The camera image may be used to determine the percentage of puddle coverage and puddling non-idealities. The camera within a fluid dispense system may also be utilized to monitor the intensity of wavelengths reflected from a substrate during a spin coating step. The reflected intensity as a function of time as a substrate is spin coated may be used to monitor and characterize a spin coating process. The reflected intensity as a function of time may be compared to other substrates to identify substrate to substrate film thickness variations. The analysis may be based upon peaks and/or troughs of the reflected intensity as a function of time.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 6, 2021
    Inventors: Michael Carcasi, Joshua Hooge, Mark Somervell, Hiroyuki Iwaki, Masahide Tadokoro, Masashi Enomoto, Joel Estrella, Yuichiro Kunugimoto
  • Publication number: 20200364109
    Abstract: A load of a data channel at the time of data writing is reduced. A memory controller includes a specific data pattern retaining unit, a comparator, and an issuance unit. The specific data pattern retaining unit retains a specific data pattern. The comparator compares write data regarding a write command from a host computer with the specific data pattern. The issuance unit issues a specific write request that requests writing of the specific data pattern without supplying the write data to a memory in a case where the write data matches the specific data pattern.
    Type: Application
    Filed: August 6, 2018
    Publication date: November 19, 2020
    Inventors: HIROYUKI IWAKI, KENICHI NAKANISHI
  • Publication number: 20200310681
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 1, 2020
    Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
  • Patent number: 10481971
    Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
  • Patent number: 10338984
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventors: Yasushi Fujinami, Kenichi Nakanishi, Tsunenori Shiimoto, Tetsuya Yamamoto, Tatsuo Shinbashi, Hideaki Okubo, Haruhiko Terada, Ken Ishii, Hiroyuki Iwaki, Matatoshi Honjo
  • Publication number: 20190056884
    Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 21, 2019
    Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
  • Patent number: 10120614
    Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 6, 2018
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Iwaki, Ken Ishii, Ryoji Ikegaya, Kenichi Nakanishi, Yasushi Fujinami, Naohiro Adachi
  • Publication number: 20180232178
    Abstract: An access speed when a memory controller accesses a memory is improved. Each time any one of two different types of commands is input, a holding unit holds the input command. A priority mode switching unit switches a priority command which should have priority out of the two commands from one of the two commands to the other. A command processing unit preferentially extracts priority commands sequentially from the holding unit, and then sequentially extracts commands which are not the priority commands from the holding unit.
    Type: Application
    Filed: June 15, 2016
    Publication date: August 16, 2018
    Inventors: Hiroyuki Iwaki, Ken Ishii, Yasushi Fujinami, Kennichi Nakanishi, Tatsuo Shinbashi
  • Publication number: 20180143871
    Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
    Type: Application
    Filed: April 15, 2016
    Publication date: May 24, 2018
    Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
  • Patent number: 9852812
    Abstract: There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 26, 2017
    Assignee: Sony Corporation
    Inventors: Hiroyuki Iwaki, Ken Ishii, Ryoji Ikegaya, Kenichi Nakanishi, Yasushi Fujinami, Naohiro Adachi
  • Publication number: 20170322842
    Abstract: Reduction in deterioration of a memory cell in a non-volatile memory is achieved. A memory controller is configured to include a time measuring unit, an elapsed time determination unit, and a read unit. The time measuring unit measures time elapsed from predetermined timing on an address where data written. The elapsed time determination unit determines whether the elapsed time exceeds a fixed amount of time upon receiving an instruction to read out the data from the address. The read control unit causes reading-out of the data from the address to pause in a case where the elapsed time is determined not to exceed the fixed amount of time.
    Type: Application
    Filed: October 8, 2015
    Publication date: November 9, 2017
    Inventors: HIROYUKI IWAKI, KEIICHI TSUTSUI, LUI SAKAI, KENICHI NAKANISHI, HIDEAKI OKUBO, YASUSHI FUJINAMI
  • Publication number: 20170255502
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Application
    Filed: July 9, 2015
    Publication date: September 7, 2017
    Inventors: YASUSHI FUJINAMI, KENICHI NAKANISHI, TSUNENORI SHIIMOTO, TETSUYA YAMAMOTO, TATSUO SHINBASHI, HIDEAKI OKUBO, HARUHIKO TERADA, KEN ISHII, HIROYUKI IWAKI, MATATOSHI HONJO
  • Publication number: 20170185478
    Abstract: The convenience of an information processing system is improved. In a memory controller of the information processing system, a request generation unit generates, with respect to a nonvolatile memory including a data area in which data is stored and a redundancy area in which a redundancy for performing error detection and error correction of the data is stored, a request of requesting writing or reading for any one of the data, and the redundancy, a code word constituted of the data and the redundancy. A control unit issues the generated request and controls writing and reading with respect to the nonvolatile memory.
    Type: Application
    Filed: June 23, 2015
    Publication date: June 29, 2017
    Applicant: SONY CORPORATION
    Inventors: LUI SAKAI, KEIICHI TSUTSUI, YASUSHI FUJINAMI, HIROYUKI IWAKI, KEN ISHII, NAOHIRO ADACHI, RYOJI IKEGAYA, KENICHI NAKANISHI
  • Publication number: 20170160952
    Abstract: A latency time of memory access is suppressed. A memory controller includes memory control units and a connection switching unit. The memory control units each independently generate a request to a memory on the basis of a command from a computer. Any one of the memory control units and the memory are connected in response to a connection request from each of the memory control units, and the request is output to the memory. A memory system is constituted of the memory and the memory controller. An information processing system is constituted of the memory system and the computer.
    Type: Application
    Filed: June 9, 2015
    Publication date: June 8, 2017
    Inventors: KENICHI NAKANISHI, HIROYUKI IWAKI, KEN ISHII, RYOJI IKEGAYA, KENTAROU MORI
  • Publication number: 20170109099
    Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.
    Type: Application
    Filed: May 19, 2015
    Publication date: April 20, 2017
    Inventors: HIROYUKI IWAKI, KEN ISHII, RYOJI IKEGAYA, KENICHI NAKANISHI, YASUSHI FUJINAMI, NAOHIRO ADACHI
  • Patent number: 9473722
    Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a column processing section that includes a low-level bit latching section. The low-level bit latching section receives a comparator output from a comparator and a count output from a counter, and the low-level bit latching section latches a count value.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: October 18, 2016
    Assignee: Sony Corporation
    Inventor: Hiroyuki Iwaki
  • Patent number: 9455017
    Abstract: A storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 27, 2016
    Assignee: Sony Corporation
    Inventors: Kenichi Nakanishi, Yasushi Fujinami, Ken Ishii, Hiroyuki Iwaki, Kentarou Mori