Abstract: A computer-implemented optimization problem arithmetic method includes receiving a combinatorial optimization problem, determining, based on scale or a requested accuracy of the combinatorial optimization problem, a partition mode and an execution mode, the partition mode defining a logically divided state of an arithmetic circuit, the execution mode defining a range of hardware resources to be utilized in arithmetic operation for each of partitions generated by logically dividing the arithmetic circuit, and causing the arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem in accordance with the determined partition mode and the determined execution mode.

Abstract: An optimization problem operation method include accepting a combinatorial optimization problem to an operation unit that is capable of being divided into a plurality of partitions logically and solving the combinatorial optimization problem. The method include deciding a partition mode that prescribes a logical division state of the operation unit and an execution mode that prescribes a range of hardware resources used in an operation in the partition mode according to a scale or a requested precision of the combinatorial optimization problem. The method include causing execution of operations of the combinatorial optimization problem in parallel in the operation unit with the partition mode and the execution mode decided, based on the number of times obtained by dividing the number of times of execution of the combinatorial optimization problem by the number of divisions corresponding to the execution mode.

Abstract: A computer-implemented optimization problem arithmetic method includes receiving a combinatorial optimization problem, determining, based on scale or a requested accuracy of the combinatorial optimization problem, a partition mode and an execution mode, the partition mode defining a logically divided state of an arithmetic circuit, the execution mode defining a range of hardware resources to be utilized in arithmetic operation for each of partitions generated by logically dividing the arithmetic circuit, and causing the arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem in accordance with the determined partition mode and the determined execution mode.

Abstract: At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.

Abstract: An information processing apparatus running multiple virtual machines includes a correspondence information storage section configured to store correspondence information between a virtual address and a physical address, the correspondence information being used by a second virtual machine when executing a procedure relevant to a first virtual machine; a correspondence information processing section configured to invalidate the correspondence information in response to an occurrence of a panic in the first virtual machine; and a preservation section configured to preserve content of a memory area allocated to the second virtual machine into a storage device.

Abstract: According to an aspect of the embodiment, a switch for information acquisition, which is included in an information processing apparatus, inputs an acquisition instruction of information for a hung-up cause investigation. A trace information acquiring unit, which is included in the information processing apparatus, acquires trace information of a first target process, which is set in a trace information setting file. A core file generating unit, which is included in the information processing apparatus, generates a core file of a second target process, which is set in a core setting file.

Abstract: At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.

Abstract: A memory protection method includes setting a memory area in at least one address setting register; setting a trap type in a trap type setting register corresponding to the address setting register; generating a trap of the trap type set in the trap type setting register in accordance with an access request to the memory area set at the address setting register; setting a size of an inaccessible area in a memory; allocating, in accordance with a memory allocation request from an application, a memory area to the application as an accessible area and an inaccessible area having the inaccessible area size right after the accessible area; setting the inaccessible area in a first address setting register and a first trap type in a first trap type setting register; and generating a memory image of the application and closing the application when a trap of the first trap type occurred.

Abstract: According to an aspect of the embodiment, a switch for information acquisition, which is included in an information processing apparatus, inputs an acquisition instruction of information for a hung-up cause investigation. A trace information acquiring unit, which is included in the information processing apparatus, acquires trace information of a first target process, which is set in a trace information setting file. A core file generating unit, which is included in the information processing apparatus, generates a core file of a second target process, which is set in a core setting file.

Abstract: The present invention writes intrinsic information such as the current time, etc. to both a memory and a storage medium when an exchangeable storage medium inserted in a drive device is mounted to a system. If the storage medium is removed from the drive device when the storage medium is being I/O accessed, then the execution of the present and the succeeding I/O requests is suspended. Then, if a storage medium is inserted in the drive device, then it is checked whether or not the intrinsic information stored in the memory has been written to the storage medium. Only when the information has been written to the storage medium, the suspended request for the storage medium is resumed. Accordingly, even if a storage medium has been erroneously removed from the drive device, all I/O requests are surely executed without being lost if the erroneously removed medium is inserted again. Furthermore, the data in a replacing storage medium won't be erroneously lost, either.