Abstract: A solar cell includes a rear surface electrode layer a semiconductor layer formed on a surface of rear surface electrode layer a front surface electrode layer formed on a surface of semiconductor layer and a support layer on a surface of rear surface electrode layer at a side opposite the side where semiconductor layer is formed. Semiconductor layer includes at least one p-n junction. A plurality of through holes are provided, which through holes are cavities connecting support layer openings provided on a surface of support layer at a side opposite the side where rear surface electrode layer is formed with semiconductor layer openings provided on a surface of semiconductor layer at a side opposite the side where rear surface electrode layer is formed. Front surface electrode layer is formed in a region where semiconductor layer openings are not provided. A method of manufacturing the solar cell is also disclosed.

Abstract: Disclosed is a stacked body for manufacturing a compound semiconductor solar battery, wherein a first etching stop layer (103) and a semiconductor stacked body (10) including at least one pn junction are arranged in this order on a semiconductor substrate (100), the semiconductor stacked body (10) has a contact layer (104) at a position in contact with the first etching stop layer, and the first etching stop layer (103) and the contact layer (104) contain a group V element of the same type.

Abstract: A concentrating solar battery in which concentrated sunlight is guided to a solar battery cell, the concentrating solar battery including: a substrate on which the solar battery cell is mounted; a light guide member disposed above the solar battery cell such that a lower surface thereof opposes the solar battery cell; and a support member that holds an upper portion of the light guide member in a hanging manner and is provided upright on the substrate, wherein the concentrating solar battery has a structure hermetically sealed by the substrate, the light guide member and the support member.

Abstract: A solar cell includes a rear surface electrode layer a semiconductor layer formed on a surface of rear surface electrode layer a front surface electrode layer formed on a surface of semiconductor layer and a support layer on a surface of rear surface electrode layer at a side opposite the side where semiconductor layer is formed. Semiconductor layer includes at least one p-n junction. A plurality of through holes are provided, which through holes are cavities connecting support layer openings provided on a surface of support layer at a side opposite the side where rear surface electrode layer is formed with semiconductor layer openings provided on a surface of semiconductor layer at a side opposite the side where rear surface electrode layer is formed. Front surface electrode layer is formed in a region where semiconductor layer openings are not provided. A method of manufacturing the solar cell is also disclosed.

Abstract: Disclosed is a method of manufacturing a photoelectric conversion element including a substrate and a stacked body configured of a plurality of compound semiconductor layers of different compositions sequentially stacked on the substrate, and having at least one pn junction in the stacked body. This method includes the steps of forming the stacked body configured of the plurality of compound semiconductor layers of different compositions sequentially stacked on the substrate; forming a protective film on the stacked body; forming a groove by removing at least a portion of the stacked body by at least one method selected from the group consisting of a mechanical removing method, dry etching and laser scribing; etching a side wall of the groove using an etching solution after forming the protective film and the groove; and cutting a portion corresponding to the groove for separation into a plurality of photoelectric conversion elements.

Abstract: In a solar cell, a body portion that includes at least one PN junction portion that is formed by laminating a P layer and an N layer in the front to back direction is formed. End faces of the PN junction portion form part of side faces of the body portion, and a surface electrode is formed on a surface of the body portion and a back surface electrode is formed on a back surface of the body portion. The surface electrode includes a terminal attachment portion to which a surface electrode connecting lead wire through which an electromotive force is extracted is bonded by wire-bonding or spot-welding. An anti-reflection film is formed on a surface of the surface electrode that includes the terminal attachment portion and the surface of the body portion other than a portion where the surface electrode is formed.

Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.

Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.

Abstract: A wiring substrate of the present invention includes a terminal section, provided on a first surface of an insulating substrate, for wire or flip-chip bondings; a land section, provided on the insulating substrate, for an external connection terminal; wiring patterns, respectively provided on the first surface and a second surface on the other side of the first surface, for making electrical connection between the terminal section and the land section; and a support pattern, provided on the second surface corresponding in position to the terminal section, for improving bondings. The wiring substrate can relieve connection failure in bondings.

Abstract: A wiring substrate of the present invention includes a terminal section, provided on a first surface of an insulating substrate, for wire or flip-chip bondings; a land section, provided on the insulating substrate, for an external connection terminal; wiring patterns, respectively provided on the first surface and a second surface on the other side of the first surface, for making electrical connection between the terminal section and the land section; and a support pattern, provided on the second surface corresponding in position to the terminal section, for improving bondings. The wiring substrate can relieve connection failure in bondings.

Abstract: In a substrate for a semiconductor device including a plurality of first through holes and a wiring pattern having a conductive land portion covering the entire surface of the opening of each of the first through holes on one surface, a second through hole is formed in a region other than the forming region of the wiring pattern, and the shape of opening of said second through hole is not a circular shape and has a corner portion.

Abstract: A resin overmolded semiconductor device includes an insulative substrate having a plurality of first through-holes, interconnection patterns provided on a chip-side surface of the insulative substrate, external connection terminals provided on the opposite surface of the insulative substrate, a semiconductor chip mounted on the chip-side surface, and a sealing portion. The insulative substrate is further formed with a plurality of second through-holes each having one end which is open on the opposite surface, and has second lands which cover the other ends of the second through-holes on the chip-side surface.

Abstract: A tape carrier for a semiconductor device comprising a flexible insulation tape having via holes for a solder ball, a metal wiring layer formed on one surface of the insulation tape, the via halls for the solder balls having an opening on the other surface of the insulating tape, and a metal brace formed on the periphery of the opening of the respective via holes, wherein the metal brace is formed in a ring-shape provided with a cutout opening having a width up to 4% of the circumferential length of the periphery, or comprises a plurality of arcuate shape portions, such that gaps are simetorically provided and positioned between the arcuate shape portions,, and that the total width of the gaps is up to 40% of the circumferential length of the periphery, and wherein the metal braces have a surface to which Ni plating is applied, and Au plating is applied to the Ni plating.

Abstract: A rectangular semiconductor chip is mounted on an insulating substrate having a plurality of first through holes the opening area of which increases toward the side of the surface of the opening, the insulating substrate is provided with a wiring pattern having conductive land portions covering the entire surface of the opening of each of the first through holes on the side of the semiconductor chip mounting surface, and an external connection terminal is connected to the entire surface of a land portion exposed from the first through hole, and the opening shape of the first through hole is a circular shape having a projected portion at least in a region including a region on a circumference the farthest from the center of the semiconductor chip.

Abstract: A semiconductor device includes an insulative substrate having a layer of interconnection patterns formed on a chip-side surface and external terminals formed on the opposite surface, and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate. In the semiconductor device, among the plurality of semiconductor chips, a semiconductor chip having the largest plan surface area has the greatest thickness.

Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.