Patents by Inventor Hiroyuki Kaigawa
Hiroyuki Kaigawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130207190Abstract: Disclosed is a semiconductor device 100 including a substrate 1, a thin film diode 10A that is supported by the substrate 1 and that includes a first semiconductor layer 13a having a p-type region 13a(p) and an n-type region 13a(n), a first wiring line RST disposed so as to overlap with the first semiconductor layer 13a of the thin film diode 10A and connected to the p-type region 13a(p), a second wiring line RWS disposed so as to overlap with the first semiconductor layer 13a of the thin film diode 10A and connected to the n-type region 13a(n), and a thin film transistor 10B that is supported by the substrate 1 that includes a second semiconductor layer 13b, a gate electrode, a source electrode, and a drain electrode. The first wiring line RST and the second wiring line RWS are formed of the same conductive film 15 as the gate electrode.Type: ApplicationFiled: October 31, 2011Publication date: August 15, 2013Applicant: SHARP KABUSHIKI KAISHAInventor: Hiroyuki Kaigawa
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Patent number: 8466020Abstract: Provided is a method of manufacturing a semiconductor device which can form a high-performance photodiode in which variation in output characteristics and performance deterioration are suppressed. A prescribed gate metal is used to form a shield section 34a that covers a portion of a first semiconductor layer 30a for a photodiode that becomes an intrinsic semiconductor region on a gate insulating film 29 and to form first to fourth gate electrodes 34b to 34e that cover portions of respective second to fifth semiconductor layers 30b to 30e for thin film transistors that become channel regions on the gate insulating film 29. Then, using the shield section 34a as a mask, an n-type region and p-type region are formed in the first semiconductor layer 30a. Then, the shield section 34a is removed.Type: GrantFiled: April 6, 2010Date of Patent: June 18, 2013Assignee: Sharp Kabushiki KaishaInventor: Hiroyuki Kaigawa
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Patent number: 8421939Abstract: A display control substrate and a method of manufacturing thereof, includes a thin film transistor (TFT) that is provided for each of a multiplicity of pixel sections provided in two dimensions and is an inversely staggered TFT. A gate electrode wiring, a Cs wiring and a source electrode wiring of the TFT are simultaneously formed. An interlayer insulation film is deposited after gate insulation films and semiconductor islands are formed. After contact holes are formed in the interlayer insulation film, at the time of forming a pixel electrode, a connecting portion for connecting cut portions of the source electrode wirings via the contact hole is formed. The source electrode wiring is connected to a source region of the semiconductor island by the connecting portion. This process reduces the number of masks required at the time of manufacturing a TFT substrate, and also reduces the lead time, increases the yield and reduces the manufacturing cost.Type: GrantFiled: December 15, 2005Date of Patent: April 16, 2013Assignee: Sharp Kabushiki KaishaInventor: Hiroyuki Kaigawa
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Publication number: 20130037903Abstract: Disclosed is a display device that is configured such that light that is emitted from a backlight or the like and that illuminates a display panel is prevented from being transmitted through a light-shielding layer that is provided between a light sensor element and a substrate. A liquid crystal display device 1 is provided with: a photodiode 10, which is formed on a substrate 30 that constitutes a part of the display panel; and a light-shielding film 20, which is formed between the substrate 30 and the photodiode 10. The thickness of the light-shielding film 20 is 100 nm or more.Type: ApplicationFiled: April 5, 2011Publication date: February 14, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Hiroyuki Kaigawa, Isao Nakanishi
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Patent number: 8357977Abstract: A method for manufacturing a semiconductor device, which includes the steps of: forming a mask layer (20) on a gate insulating film (18), the mask layer (20) having openings over the portions of first and second semiconductor layers that are destined to become low-concentration impurity regions and source and drain regions; forming first conductivity type implantation regions (24b, 24c) in the first and second semiconductor layers respectively by implanting a first conductivity type impurity (22) to the first and second semiconductor layers through the openings in the mask layer (20); forming first and second gate electrodes (26b, 26c) to cover a portion of the first conductivity type implantation regions and portions of the first and second semiconductor layers that are destined to become channel regions; forming another mask layer (28) which has openings over portions of the first conductivity type implantation region (24b) of the first semiconductor layer, said portions being located at both ends of the fiType: GrantFiled: October 22, 2009Date of Patent: January 22, 2013Assignee: Sharp Kabushiki KaishaInventor: Hiroyuki Kaigawa
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Publication number: 20120256304Abstract: This semiconductor device includes: a substrate; and a plurality of thin-film diodes which are supported by the substrate and electrically connected in parallel with each other. The thin-film diodes include at least one thin-film diode of a first type (100A), of which the semiconductor layer (10A) has an N-type region (1A), an intrinsic region (5A), and a P-type region (3A) that are arranged in this order in a first direction X within a plane that is parallel to the substrate, and at least one thin-film diode of a second type (100B), of which the semiconductor layer (10B) has a P-type region (3B), an intrinsic region (5B), and an N-type region (1B) that are arranged in this order in the first direction X. With such a configuration adopted, the variation in photocurrent characteristic between the thin-film diodes can be reduced.Type: ApplicationFiled: November 11, 2010Publication date: October 11, 2012Applicant: SHARP KABUSHIKI KAISHAInventor: Hiroyuki Kaigawa
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Patent number: 8243032Abstract: A touch panel includes an insulating substrate, a transparent touch electrode provided on the insulating substrate, and a frame portion connected to a periphery of the touch electrode. The touch panel detects a touched position on the touch electrode based on an electric signal through the frame portion. The frame portion is provided between the insulating substrate and the touch electrode.Type: GrantFiled: January 31, 2007Date of Patent: August 14, 2012Assignee: Sharp Kabushiki KaishaInventors: Shogo Nishiwaki, Yoshiharu Kataoka, Toru Daito, Shinya Tanaka, Yukihiko Nishiyama, Shingo Kawashima, Hiroyuki Kaigawa, Takayuki Urabe
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Publication number: 20120058589Abstract: Provided is a method of manufacturing a semiconductor device which can form a high-performance photodiode in which variation in output characteristics and performance deterioration are suppressed. A prescribed gate metal is used to form a shield section 34a that covers a portion of a first semiconductor layer 30a for a photodiode that becomes an intrinsic semiconductor region on a gate insulating film 29 and to form first to fourth gate electrodes 34b to 34e that cover portions of respective second to fifth semiconductor layers 30b to 30e for thin film transistors that become channel regions on the gate insulating film 29. Then, using the shield section 34a as a mask, an n-type region and p-type region are formed in the first semiconductor layer 30a. Then, the shield section 34a is removed.Type: ApplicationFiled: April 6, 2010Publication date: March 8, 2012Applicant: SHARP KABUSHIKI KAISHAInventor: Hiroyuki Kaigawa
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Publication number: 20110193168Abstract: A method for manufacturing a semiconductor device, which includes the steps of: forming a mask layer (20) on a gate insulating film (18), the mask layer (20) having openings over the portions of first and second semiconductor layers that are destined to become low-concentration impurity regions and source and drain regions; forming first conductivity type implantation regions (24b, 24c) in the first and second semiconductor layers respectively by implanting a first conductivity type impurity (22) to the first and second semiconductor layers through the openings in the mask layer (20); forming first and second gate electrodes (26b, 26c) to cover a portion of the first conductivity type implantation regions and portions of the first and second semiconductor layers that are destined to become channel regions; forming another mask layer (28) which has openings over portions of the first conductivity type implantation region (24b) of the first semiconductor layer, said portions being located at both ends of the fiType: ApplicationFiled: October 22, 2009Publication date: August 11, 2011Applicant: SHARP KABUSHIKI KAISHAInventor: Hiroyuki Kaigawa
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Patent number: 7750349Abstract: A switching element substrate for a liquid crystal display device for transmissive display includes an insulating substrate, and a plurality of switching elements formed on one of surfaces of the insulating substrate. A transmitting region is defined on an exposed part of the other surface of the insulating substrate. Each of the switching elements includes a monocrystalline silicon layer.Type: GrantFiled: August 10, 2005Date of Patent: July 6, 2010Assignee: Sharp Kabushiki KaishaInventor: Hiroyuki Kaigawa
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Publication number: 20100053114Abstract: A touch panel apparatus includes a position detection electrode formed in a touch region and made of ITO, and a wiring portion provided in a frame region and electrically connected to the position detection electrode. The wiring portion has a first pattern film extended from the position detection electrode and made of ITO, a second pattern film laminated on the first pattern film and made of IZO, and a third pattern film laminated on the second pattern film and made of silver or a silver alloy.Type: ApplicationFiled: October 31, 2007Publication date: March 4, 2010Inventor: Hiroyuki Kaigawa
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Publication number: 20090303214Abstract: A display control substrate and a method of manufacturing thereof, includes a thin film transistor (TFT) that is provided for each of a multiplicity of pixel sections provided in two dimensions and is an inversely staggered TFT. A gate electrode wiring, a Cs wiring and a source electrode wiring of the TFT are simultaneously formed. An interlayer insulation film is deposited after gate insulation films and semiconductor islands are formed. After contact holes are formed in the interlayer insulation film, at the time of forming a pixel electrode, a connecting portion for connecting cut portions of the source electrode wirings via the contact hole is formed. The source electrode wiring is connected to a source region of the semiconductor island by the connecting portion. This process reduces the number of masks required at the time of manufacturing a TFT substrate, and also reduces the lead time, increases the yield and reduces the manufacturing cost.Type: ApplicationFiled: December 15, 2005Publication date: December 10, 2009Applicant: SHARP KABUSHIKI KAISHAInventor: Hiroyuki Kaigawa
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Publication number: 20090096759Abstract: A touch panel includes an insulating substrate, a transparent touch electrode provided on the insulating substrate, and a frame portion connected to a periphery of the touch electrode. The touch panel detects a touched position on the touch electrode based on an electric signal through the frame portion. The frame portion is provided between the insulating substrate and the touch electrode.Type: ApplicationFiled: January 31, 2007Publication date: April 16, 2009Inventors: Shogo Nishiwaki, Yoshiharu Kataoka, Toru Daito, Shinya Tanaka, Yukihiko Nishiyama, Shingo Kawashima, Hiroyuki Kaigawa, Takayuki Urabe
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Publication number: 20060033855Abstract: A switching element substrate for a liquid crystal display device for transmissive display includes an insulating substrate, and a plurality of switching elements formed on one of surfaces of the insulating substrate. A transmitting region is defined on an exposed part of the other surface of the insulating substrate. Each of the switching elements includes a monocrystalline silicon layer.Type: ApplicationFiled: August 10, 2005Publication date: February 16, 2006Inventor: Hiroyuki Kaigawa
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Patent number: 5506155Abstract: It is an object of the present invention to provide a method for manufacturing a substrate for a semiconductor device which can increase efficiency of production of the substrate for a semiconductor device, and a method for manufacturing a substrate which can be utilized to produce a highly integrated semiconductor device. A polysilicon layer is formed on both the top surface and the bottom surface of the wafer (see FIG. 4B), before removing the polysilicon layer from the top surface of the wafer (see FIG. 4C). The polysilicon layer which remains on the bottom surface of the wafer is selectively removed, except in the device formation region (see FIG. 4D). Impurities (such as Fe or the like) contained in the wafer are trapped in distortion ST50 and distortion ST60 which occur between the wafer and the polysilicon layer. Since the polysilicon layer is formed separately on the bottom surface of the wafer, the tensile stress of the polysilicon layer is released.Type: GrantFiled: January 21, 1994Date of Patent: April 9, 1996Assignee: Rohm Co., Ltd.Inventor: Hiroyuki Kaigawa
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Patent number: 5468675Abstract: Method for manufacturing a device separation region for semiconductor devices which separates regions electrically from each other stably, and allows realization of large scale integration with high reliability. When forming a device separation region 10 selectively on a substrate 1 by LOCOS method by controlling thermal oxidation, a device separation region 10 is formed to thickness t2 thinner than a predetermined thickness (FIG. 4C). A second silicon nitride layer 5 is formed onto the whole surface of the substrate 1 (FIG. 5A). A photo resist layer 8 is formed on the second silicon nitride layer 5, and the second silicon nitride layer 5 is partially removed by chemical etching (FIG. 5B). By carrying out thermal oxidation again after the etching, the device separation region 10 is formed to the predetermined thickness t (FIG. 5C). In that, device separation is accomplished stably.Type: GrantFiled: May 26, 1994Date of Patent: November 21, 1995Assignee: Rohm Co., Ltd.Inventor: Hiroyuki Kaigawa