Patents by Inventor Hiroyuki Kamada

Hiroyuki Kamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240138690
    Abstract: An arrhythmic state detection assisting device includes an acquisition unit, a derivation unit and an estimation unit. The acquisition unit acquires image information obtained by capturing an image of a predetermined part of a subject with an image capture device that captures a color moving image. The derivation unit derives a variance value, for a predetermined interval, of periods of a periodic change in a green luminance component in the image information acquired by the acquisition unit. As the variance value derived by the derivation unit becomes greater, the estimation unit estimates a higher likelihood that an arrhythmia is occurring in the subject.
    Type: Application
    Filed: December 21, 2021
    Publication date: May 2, 2024
    Applicant: Astellas Pharma Inc.
    Inventors: Makoto OGINO, Hiroyuki KAMADA
  • Publication number: 20240141548
    Abstract: The present invention is a single crystal pulling apparatus which includes a pulling furnace having a central axis and a magnetic field generating apparatus having coils, and applies a horizontal magnetic field to a molten semiconductor raw material, wherein the coils are saddle-shaped, two pairs of the coils are provided with the coils of each pair arranged facing each other, two coil axes in the two pairs of coils are included in the same horizontal plane, when a magnetic force line direction on the central axis of the pulling furnace in the horizontal plane is defined as a X-axis, and a direction perpendicular to the X-axis in the horizontal plane is defined as a Y-axis, a center angle ? between the two coil axes sandwiching the X-axis is 90 degrees or less and an inter-coil angle ? between adjacent superconducting coils sandwiching the Y-axis is 20 degrees or less.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 2, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyotaka TAKANO, Hiroyuki KAMADA
  • Publication number: 20240076800
    Abstract: A single crystal pulling apparatus includes: a pulling furnace having a central axis; and magnetic field generating apparatus around the pulling furnace and having coils, for applying a horizontal magnetic field to molten semiconductor raw material to suppress convection in crucible, in which, main coils and sub-coils are provided, as the main coils, two pairs of coils arranged facing each other are provided, two coil axes thereof are included in the same horizontal plane, a center angle ? between the two coil axes sandwiching the X-axis, which is a magnetic force line direction on the central axis in the horizontal plane, is 100 degrees or more and 120 degrees or less, as the sub-coils, a pair of superconducting coils arranged to face each other is provided and its one coil axis is aligned with the X-axis, and current values of the main coils and the sub-coils can be set independently.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 7, 2024
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroyuki KAMADA, Kiyotaka TAKANO
  • Publication number: 20230175166
    Abstract: The present invention is a single-crystal pulling apparatus including: a pulling furnace which has a heater and a crucible arranged and which has a central axis; and a magnetic field generation device having superconducting coils, where the magnetic field generation device has four of the superconducting coils, two of the superconducting coils are arranged in each of two regions divided by a cross section that includes an X axis, the X axis being a direction of lines of magnetic force at the central axis in the horizontal plane including all the coil axes of the four superconducting coils, and includes the central axis of the pulling furnace so as to have line symmetry about the cross section, the four superconducting coils are all arranged so that the coil axes have an angle within a range of more than ?30° and less than 30° relative to a Y axis, the direction of the lines of magnetic force thereof have line symmetry about the cross section, and in each of the regions, the two superconducting coils generate
    Type: Application
    Filed: March 19, 2020
    Publication date: June 8, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyotaka TAKANO, Wataru YAJIMA, Kosei SUGAWARA, Hiroyuki KAMADA, Tomohiko OHTA
  • Publication number: 20230138632
    Abstract: A single-crystal pulling apparatus including: a pulling furnace having a central axis; and a magnetic field generation device arranged around the pulling furnace and having superconducting coils, the apparatus applying a horizontal magnetic field to the molten semiconductor raw material, two coil axes in the two pairs of the superconducting coils are included in a single horizontal plane, and when a direction of lines of magnetic force at the central axis of the pulling furnace in the horizontal plane is determined as an X axis, a center angle ? having the X axis between the two coil axes is 100 degrees or more and 120 degrees or less. This makes it possible to reduce the height of the coils, to raise the magnetic field center close to the melt surface of the semiconductor raw material, and to obtain a single crystal having a lower oxygen concentration than conventional single crystals.
    Type: Application
    Filed: February 22, 2021
    Publication date: May 4, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyotaka TAKANO, Kosei SUGAWARA, Hiroyuki KAMADA, Takahide ONAI, Tomohiko OHTA
  • Patent number: 11081556
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating layer provided on a surface of the silicon carbide substrate, a gate electrode provided on the gate insulating layer, a first insulting layer provided on the gate electrode, a first layer provided on the first insulating layer, a second insulating layer provided on the first insulating layer, and an interconnect layer provided on the second insulating layer. The second insulating layer includes SiN or SiON. The first layer includes one of Ti, TiN, Ta, and TaN. The interconnect layer includes Al or Cu.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 3, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hiroyuki Kamada
  • Publication number: 20200251564
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating layer provided on a surface of the silicon carbide substrate, a gate electrode provided on the gate insulating layer, a first insulting layer provided on the gate electrode, a first layer provided on the first insulating layer, a second insulating layer provided on the first insulating layer, and an interconnect layer provided on the second insulating layer. The second insulating layer includes SiN or SiON. The first layer includes one of Ti, TiN, Ta, and TaN. The interconnect layer includes Al or Cu.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 6, 2020
    Inventor: Hiroyuki KAMADA
  • Patent number: 10400353
    Abstract: A method controls a resistivity of a grown silicon single crystal by using a dopant when the silicon single crystal is grown by CZ method, including the steps of initially doping with a primary dopant such that the silicon single crystal has a predetermined conductive type and additionally doping with a secondary dopant having a conductive type opposite to that of the primary dopant continuously or intermittently, according to a solidification rate expressed by (crystalized weight)/(initial weight of silicon raw material) while growing the silicon single crystal, wherein in the additional doping step, the additional doping with the secondary dopant is carried out when the solidification rate is a predetermined value ? or more, while the crystal is not doped with the secondary dopant until the solidification rate reaches the predetermined value ?.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: September 3, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada, Kiyotaka Takano
  • Patent number: 10066322
    Abstract: A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: September 4, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada
  • Patent number: 9938640
    Abstract: The present invention is a method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a void size in the silicon single crystal wafer before the heat treatment. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: April 10, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada
  • Patent number: 9850595
    Abstract: A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.
    Type: Grant
    Filed: August 1, 2015
    Date of Patent: December 26, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada
  • Publication number: 20170342596
    Abstract: A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: Ryoji HOSHI, Hiroyuki KAMADA
  • Patent number: 9773710
    Abstract: A method for evaluating concentration of defect in silicon single crystal substrate, defect being formed by particle beam irradiation in silicon single crystal substrate, including the steps of: measuring a resistivity of silicon single crystal substrate, followed by irradiating silicon single crystal substrate with particle beam, re-measuring resistivity of silicon single crystal substrate after irradiation; determining each carrier concentration in silicon single crystal substrate before and after irradiation on basis of measured results of resistivity before and after particle beam irradiation to calculate rate of change of carrier concentration; and evaluating concentration of VV defect on basis of rate of change of carrier concentration, VV defect being made of a silicon atom vacancy and being formed by particle beam irradiation in silicon single crystal substrate. The method can simply evaluate concentration of VV defect formed in silicon single crystal substrate by particle beam irradiation.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 26, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroyuki Kamada, Ryoji Hoshi
  • Publication number: 20170260645
    Abstract: A method controls a resistivity of a grown silicon single crystal by using a dopant when the silicon single crystal is grown by CZ method, including the steps of initially doping with a primary dopant such that the silicon single crystal has a predetermined conductive type and additionally doping with a secondary dopant having a conductive type opposite to that of the primary dopant continuously or intermittently, according to a solidification rate expressed by (crystalized weight)/(initial weight of silicon raw material) while growing the silicon single crystal, wherein in the additional doping step, the additional doping with the secondary dopant is carried out when the solidification rate is a predetermined value ? or more, while the crystal is not doped with the secondary dopant until the solidification rate reaches the predetermined value ?.
    Type: Application
    Filed: August 14, 2015
    Publication date: September 14, 2017
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji HOSHI, Hiroyuki KAMADA, Kiyotaka TAKANO
  • Patent number: 9650725
    Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, wherein, under a growth condition that V/G?1.05×(V/G)crt is achieved where V is a growth rate in growth of the silicon single crystal ingot, G is a temperature gradient near a crystal growth interface, and (V/G)crt is a value of V/G when a dominant point defect changes from a vacancy to interstitial Si, a silicon single crystal ingot having oxygen concentration of 7×1017 atoms/cm3 (ASTM'79) or less is grown, and a silicon single crystal wafer which includes a region where the vacancy is dominant and in which FPDs are not detected by preferential etching is manufactured from the grown silicon single crystal ingot. As a result, there is provided the method that enables manufacturing a low-oxygen concentration silicon single crystal wafer that can be preferably used for a power device with good productivity at a low cost.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: May 16, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada, Kosei Sugawara
  • Publication number: 20170037541
    Abstract: A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.
    Type: Application
    Filed: August 1, 2015
    Publication date: February 9, 2017
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji HOSHI, Hiroyuki KAMADA
  • Publication number: 20170002480
    Abstract: The present invention is a method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a void size in the silicon single crystal wafer before the heat treatment. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.
    Type: Application
    Filed: January 8, 2015
    Publication date: January 5, 2017
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji HOSHI, Hiroyuki KAMADA
  • Publication number: 20160300768
    Abstract: A method for evaluating concentration of defect in silicon single crystal substrate, defect being formed by particle beam irradiation in silicon single crystal substrate, including the steps of: measuring a resistivity of silicon single crystal substrate, followed by irradiating silicon single crystal substrate with particle beam, re-measuring resistivity of silicon single crystal substrate after irradiation; determining each carrier concentration in silicon single crystal substrate before and after irradiation on basis of measured results of resistivity before and after particle beam irradiation to calculate rate of change of carrier concentration; and evaluating concentration of VV defect on basis of rate of change of carrier concentration, VV defect being made of a silicon atom vacancy and being formed by particle beam irradiation in silicon single crystal substrate. The method can simply evaluate concentration of VV defect formed in silicon single crystal substrate by particle beam irradiation.
    Type: Application
    Filed: November 12, 2014
    Publication date: October 13, 2016
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroyuki KAMADA, Ryoji HOSHI
  • Patent number: 9111883
    Abstract: The present invention provides a method for evaluating silicon single crystal wherein an amount ?[C] of carriers generated due to oxygen donors produced when a heat treatment is performed to the silicon single crystal is calculated and evaluated, the amount ?[C] being calculated from oxygen concentration [Oi] in the silicon single crystal, a temperature T of the heat treatment, a time t of the heat treatment, and an oxygen diffusion coefficient D(T) at the temperature T by using the following relational expression: ?[C]=?[Oi]5×exp(??·D(T)·[Oi]·t) (where ? and ? are constants). As a result, there is provided a method that enables evaluating an amount of carriers generated due to oxygen donors in silicon single crystal in a further versatile manner.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: August 18, 2015
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada, Suguru Matsumoto
  • Publication number: 20150020728
    Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, wherein, under a growth condition that V/G?1.05×(V/G)crt is achieved where V is a growth rate in growth of the silicon single crystal ingot, G is a temperature gradient near a crystal growth interface, and (V/G)crt is a value of V/G when a dominant point defect changes from a vacancy to interstitial Si, a silicon single crystal ingot having oxygen concentration of 7×1017 atoms/cm3 (ASTM'79) or less is grown, and a silicon single crystal wafer which includes a region where the vacancy is dominant and in which FPDs are not detected by preferential etching is manufactured from the grown silicon single crystal ingot. As a result, there is provided the method that enables manufacturing a low-oxygen concentration silicon single crystal wafer that can be preferably used for a power device with good productivity at a low cost.
    Type: Application
    Filed: February 15, 2013
    Publication date: January 22, 2015
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada, Kosei Sugawara