Patents by Inventor Hiroyuki Kanata

Hiroyuki Kanata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7663187
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: February 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • Patent number: 7585739
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: September 8, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • Publication number: 20080206948
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Application
    Filed: November 21, 2007
    Publication date: August 28, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • Publication number: 20080203475
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Application
    Filed: November 21, 2007
    Publication date: August 28, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • Patent number: 7321151
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: January 22, 2008
    Assignee: Fujitsu Limited
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • Publication number: 20050095765
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Application
    Filed: March 16, 2004
    Publication date: May 5, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • Patent number: 6033134
    Abstract: In the production of semiconductor devices, a pattern-wise exposed resist coating is developed with a developer to form a resist pattern corresponding to the pattern of exposure radiation on an article to be fabricated. The development being carried out with a developer consisting of one or more organic solvents, in at least two stages and in each stage of the development, the development is interrupted when a substantial permeation of the developer of a surface portion of the pattern-forming area of the resist pattern in which the resist pattern remains is completed, and the developed resist coating is dried between this stage and the following development stages. The development of the exposed resist coating is carried out by using a developing apparatus which comprises at least one set of developer-supplying system and rinsing solution-supplying system, and a conveyor means for guiding the article carrying the resist coating.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: March 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Takashi Maruyama, Tatsuo Chijimatsu, Koichi Kobayashi, Keiko Yano, Hiroyuki Kanata
  • Patent number: 5783367
    Abstract: In the production of semiconductor devices, a pattern-wise exposed resist coating is developed with a developer to form a resist pattern corresponding to the pattern of exposure radiation on an article to be fabricated. The development being carried out with a developer consisting of one or more organic solvents, in at least two stages and in each stage of the development, the development is interrupted when a substantial permeation of the developer of a surface portion of the pattern-forming area of the resist pattern in which the resist pattern remains is completed, and the developed resist coating is dried between this stage and the following development stages. The development of the exposed resist coating is carried out by using a developing apparatus which comprises at least one set of developer-supplying system and rinsing solution-supplying system, and a conveyor means for guiding the article carrying the resist coating.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: July 21, 1998
    Assignee: Fujitsu Limited
    Inventors: Takashi Maruyama, Tatsuo Chijimatsu, Koichi Kobayashi, Keiko Yano, Hiroyuki Kanata
  • Patent number: 5667923
    Abstract: A subject pattern and a lower layer pattern are divided into small regions of a constant dimension using identical mesh of division. Considering of the spreading of charged particle beam due to backward scattering, the small region is set to be, for example, a few .mu.m square. An irradiation energy on each small region is determined by taking backward scattering from lower level pattern into account. Calculation is simplified because a pattern is represented by a pattern areal density. A region with a lower level pattern and a region without a lower level pattern can be exposured by charged particle beam with a comparable accuracy.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: September 16, 1997
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Kanata