Patents by Inventor Hiroyuki Kida
Hiroyuki Kida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9622140Abstract: A base station performs communication with a terminal by using a cell defined as a combination of a frequency and an area reachable by a signal transmitted from the base station. The base station specifies, for each of cells, a first area in which disconnection of communication with a terminal occurs more frequently as compared to another area. The base station controls handover that changes a current cell of a first terminal to another cell, based on information on the specified first area and the current cell of the first terminal, and a position, moving speed, and moving direction of the first terminal.Type: GrantFiled: October 22, 2013Date of Patent: April 11, 2017Assignee: FUJITSU LIMITEDInventors: Hiroyuki Kida, Kenichi Nunokawa, Shoichiro Ebesu
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Patent number: 9351188Abstract: A wireless base station device includes a broadcast signal transmission unit that transmits a broadcast signal to a cell; a measurement signal communication unit that transmits to a mobile terminal device existing in the cell a measurement instruction signal and receives a measurement report signal from the mobile terminal device; a failure detection processing unit that detects a failure of a first cell with respect to a transmission function from the wireless base station to the first cell according to whether a measurement report signal including a measurement report of a wireless quality for a second cell measured by a mobile terminal device existing in a coverage area of the first cell is received or not; and an alarm signal transmission unit that transmits an alarm signal to notify a failure monitoring device of an occurrence of the failure of the first cell.Type: GrantFiled: December 4, 2014Date of Patent: May 24, 2016Assignee: FUJITSU LIMITEDInventors: Kenichi Nunokawa, Hiroyuki Kida
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Publication number: 20150201341Abstract: A wireless base station device includes a broadcast signal transmission unit that transmits a broadcast signal to a cell; a measurement signal communication unit that transmits to a mobile terminal device existing in the cell a measurement instruction signal and receives a measurement report signal from the mobile terminal device; a failure detection processing unit that detects a failure of a first cell with respect to a transmission function from the wireless base station to the first cell according to whether a measurement report signal including a measurement report of a wireless quality for a second cell measured by a mobile terminal device existing in a coverage area of the first cell is received or not; and an alarm signal transmission unit that transmits an alarm signal to notify a failure monitoring device of an occurrence of the failure of the first cell.Type: ApplicationFiled: December 4, 2014Publication date: July 16, 2015Inventors: Kenichi NUNOKAWA, Hiroyuki KIDA
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Publication number: 20140155073Abstract: A base station performs communication with a terminal by using a cell defined as a combination of a frequency and an area reachable by a signal transmitted from the base station. The base station specifies, for each of cells, a first area in which disconnection of communication with a terminal occurs more frequently as compared to another area. The base station controls handover that changes a current cell of a first terminal to another cell, based on information on the specified first area and the current cell of the first terminal, and a position, moving speed, and moving direction of the first terminal.Type: ApplicationFiled: October 22, 2013Publication date: June 5, 2014Applicant: FUJITSU LIMITEDInventors: Hiroyuki Kida, Kenichi NUNOKAWA, Shoichiro EBESU
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Patent number: 8391867Abstract: A first base station apparatus, when newly installed, extracts cells of a second base station apparatus and its coverage cells neighboring them from neighboring cell information stored therein. The first base station apparatus notifies the second base station apparatus of the cells by a notification message. The second base station apparatus updates neighboring cell information stored therein based on the notification message. The first base station apparatus also sends a notification message to a third base station apparatus so that the third base station apparatus updates neighboring cell information stored therein.Type: GrantFiled: January 22, 2009Date of Patent: March 5, 2013Assignee: Fujitsu LimitedInventors: Hiroyuki Kida, Hiroshi Ohiwane
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Publication number: 20090280811Abstract: A first base station apparatus, when newly installed, extracts cells of a second base station apparatus and its coverage cells neighboring them from neighboring cell information stored therein. The first base station apparatus notifies the second base station apparatus of the cells by a notification message. The second base station apparatus updates neighboring cell information stored therein based on the notification message. The first base station apparatus also sends a notification message to a third base station apparatus so that the third base station apparatus updates neighboring cell information stored therein.Type: ApplicationFiled: January 22, 2009Publication date: November 12, 2009Inventors: Hiroyuki Kida, Hiroshi Ohiwane
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Publication number: 20070125568Abstract: A water swelling water stop material comprised of a water permeable sheet, characterized in that water absorbent resin particles (A) are enclosed therein so that the water stop material upon water absorption and swelling has the configuration of polyhedron (B). The water stop material is thin to thereby facilitate storage thereof and is lightweight to thereby render carry thereof easy. The polyhedron (B) is so constructed that upon water absorption and swelling, at least two faces are planar. When the polyhedron (B) is formed into a rectangular solid or cube, even if multiple polyhedrons (B) are piled one upon another, they are stable and are resistant to collapse even under the influence of a a large amount of water. When polyhedrons (B) of the same configuration are piled one upon another, any gaps between water stop materials are slight so as to inhibit water leakage through the gaps.Type: ApplicationFiled: January 27, 2005Publication date: June 7, 2007Inventors: Hiroyuki Kida, Yukio Zenitani
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Publication number: 20060007938Abstract: Internet Protocol (IP) telephone number information system performs for the telephone number in the existing communication systems. A number information server in the system has a region information database representing an IP telephony service area for each of a plurality of Internet Service Providers (ISPs) having a corporate information database. The number information server specifies one of the plurality of ISPs from the region information database, based on a search condition input from a user terminal connected to the Internet. The specified ISP searches the corresponding corporate information database, and obtains number information matching the search condition. The number information server notifies the user terminal of the number information obtained from searching the corporate information database, in response to the search condition input from the user terminal.Type: ApplicationFiled: December 8, 2004Publication date: January 12, 2006Inventors: Shouichi Kimura, Kazutoshi Kobayashi, Jun Ito, Hiroyuki Kida, Tatsuya Fukuyo, Sachito Shibata, Koichiro Hojyo, Naomi Ojima, Michiko Osawa, Akira Yonenaga, Hirotomo Yasuoka, Takashi Ueno
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Patent number: 6895432Abstract: An IP communication network system has a plurality of autonomous systems, configuring IP networks of domains independent of each other, for performing interior- and exterior-forwarding of IP packets. The plurality of autonomous systems include a plurality of border relay devices positioned at borders between the IP networks. Each of the plurality of border relay devices includes a discarding unit for discarding, if the IP packet forwarded is an unauthorized intrusion packet, this unauthorized packet when detecting a re-intrusion on the basis of filtering information for detecting the re-intrusion of the unauthorized packet, and a distribution unit for distributing the filtering information to all other border relay devices within the same autonomous system.Type: GrantFiled: May 4, 2001Date of Patent: May 17, 2005Assignee: Fujitsu LimitedInventors: Tadanao Ando, Atsuko Taguchi, Tatsuo Kondou, Hiroyuki Kida
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Publication number: 20020078202Abstract: An IP communication network system has a plurality of autonomous systems, configuring IP networks of domains independent of each other, for performing interior- and exterior-forwarding of IP packets. The plurality of autonomous systems include a plurality of border relay devices positioned at borders between the IP networks. Each of the plurality of border relay devices includes a discarding unit for discarding, if the IP packet forwarded is an unauthorized intrusion packet, this unauthorized packet when detecting a re-intrusion on the basis of filtering information for detecting the re-intrusion of the unauthorized packet, and a distribution unit for distributing the filtering information to all other border relay devices within the same autonomous system.Type: ApplicationFiled: May 4, 2001Publication date: June 20, 2002Inventors: Tadanao Ando, Atsuko Taguchi, Tatsuo Kondou, Hiroyuki Kida
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Patent number: 6249837Abstract: A memory is configured such that two operational modes, including a high-speed access mode in which current dissipation amount is large, but a high-speed access is possible, and a small current mode in which an access speed is lower than that in said high-speed access mode, but the current dissipation amount is small, are provided in the memory. The memory includes a control circuit for executing one of the two operational modes for the memory, in accordance with a mode designation signal sent from the outside of the memory.Type: GrantFiled: October 24, 1997Date of Patent: June 19, 2001Assignee: Hitachi, Ltd.Inventors: Masahiro Tsuchiya, Masaru Sugai, Hiroyuki Kida
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Patent number: 6198334Abstract: In a CMOS noise eliminating circuit, a plurality of PMOS transistors or NMOS transistors are connected in series so as to cause of switching speeds or switching timings of the PMOS transistors or the NMOS transistors, which are connected in series, to differ from each other, thereby improving the noise-resistant performance of a semiconductor integrated circuit.Type: GrantFiled: April 24, 1998Date of Patent: March 6, 2001Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Koichi Tomobe, Masaru Sugai, Hiroyuki Kida, Masahiro Tsuchiya, Yuji Matsushita, Hideto Suzuki
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Patent number: 6169794Abstract: In an IN where the same service is provided by a plurality of SCPs, data consistency is maintained when an update occurs to subscriber data as a result of processing a service for a subscriber. When an update is made to a subscriber database in an SCP, update information is sent to the other SCPs by way of a route selected from among a route via a common channel signaling network, a route via a LAN, and a route via an SMS. Updates occurring during backup or restore processing on a main subscriber database in the SMS are accumulated within the SMS, and the accumulated updates are applied to the main subscriber database after completion of the processing.Type: GrantFiled: May 13, 1998Date of Patent: January 2, 2001Assignee: Fujitsu LimitedInventors: Kiyoshi Oshimi, Hiroyuki Kida, Masaki Watanabe, Shinichi Kozuka
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Patent number: 5956263Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.Type: GrantFiled: January 31, 1997Date of Patent: September 21, 1999Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida, Mitsuru Watabe, Tetsuaki Nakamikawa, Shunpei Kawasaki, Junichi Tatezaki, Norio Nakagawa, Yugo Kashiwagi
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Patent number: 5644703Abstract: A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.Type: GrantFiled: November 7, 1995Date of Patent: July 1, 1997Assignee: Hitachi, Ltd.Inventors: Keiichi Kurakazu, Yoshikazu Aoto, Shiro Baba, Satoshi Masuda, Hiroyuki Kida, Shinji Kawashima, Yoshiaki Naruse
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Patent number: 5642499Abstract: In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.Type: GrantFiled: April 6, 1994Date of Patent: June 24, 1997Assignee: Hitachi, Ltd.Inventors: Mamoru Ohba, Shigeki Morinaga, Mitsuru Watabe, Hiroyuki Kida
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Patent number: 5631858Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.Type: GrantFiled: August 12, 1993Date of Patent: May 20, 1997Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida, Mitsuru Watabe, Tetsuaki Nakamikawa, Shunpei Kawasaki, Junichi Tatezaki, Norio Nakagawa, Yugo Kashiwagi
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Patent number: 5524087Abstract: A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.Type: GrantFiled: January 3, 1995Date of Patent: June 4, 1996Assignee: Hitachi, Ltd.Inventors: Masanobu Kawamura, Hiroyuki Kida, Seiji Kamada, Toshiyuki Tojo, Takeshi Ohkubo, Hiroyuki Matsuura, Naoki Yashiki, Nobuo Shibasaki
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Patent number: 5504912Abstract: The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.Type: GrantFiled: February 5, 1992Date of Patent: April 2, 1996Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Shigeki Morinaga, Norio Nakagawa, Mitsuru Watabe, Mamoru Ohba, Hiroyuki Kida, Hisashi Kaziwara, Takeshi Asai, Junichi Tatezaki
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Patent number: 5493659Abstract: A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.Type: GrantFiled: December 13, 1990Date of Patent: February 20, 1996Assignee: Hitachi, Ltd.Inventors: Keiichi Kurakazu, Yoshikazu Aoto, Shiro Baba, Satoshi Masuda, Hiroyuki Kida, Shinji Kawashima, Yoshiaki Naruse