Patents by Inventor Hiroyuki Kitajima

Hiroyuki Kitajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6108750
    Abstract: A disk storage system has a control unit having a plurality of external connection points. When the control unit receives two read requests issued from a processor to two disks of a disk unit group, a first read operation is performed to read data requested by the first read request from one of the disks and a second read operation is performed to read data requested by the second read request from the other one of the disks. Also, a first output operation is performed to output data read by the first read operation from one of the external connection points of the control unit and a second output operation is performed to output data read by the second read operation from another of the external connection points of the control unit. The second output operation is started before the first output operation has finished.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: August 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 6085286
    Abstract: In an information processing system having a data processing apparatus, a control unit for a cache memory, and a storage unit for storing a record, respectively interconnected together, wherein when the control unit receives from the data processing apparatus a write request for a record to be written and if the record to be written is not being stored in the cache memory, the control unit receives a data to be written in the object record from the data processing apparatus and stores the received data in the cache memory. After notifying the data processing apparatus of a completion of a data write process, the control unit checks if the object record in which the data stored in the cache memory is being stored in the storage unit, if the object record is being stored in the storage unit, the data in the cache memory is written in the storage unit, and if not, the data in the cache memory is not written and such effect is notified to the data processing apparatus.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: July 4, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Shigeo Homma, Yoshihiro Asaka, Yoshiaki Kuwahara, Akira Kurano, Masafumi Nozawa, Hiroyuki Kitajima
  • Patent number: 5917999
    Abstract: When receiving a write request from a processor, a control unit checks the condition of existence (or the presence/absence) in a cache for information necessary for generation of an updated value of a parity record, receives write data and reports the completion of the write request to the processor. In asynchronism with the write request from the processor, the control unit performs a load process for that information among the information necessary for generation of the updated value of the parity record which may be prepared in asynchronism with the write request from the processor and a write after process for the updated value of the parity record.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: June 29, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Hiroyuki Kitajima, Kouji Arai, Yoshihisa Kamo
  • Patent number: 5835938
    Abstract: For a write request from the CPU, the control unit selects a specific disk unit in the disk unit group for the immediate writing of data. In a second kind of load distribution a disk unit is selected to execute read and staging other than the above-mentioned specific disk.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: November 10, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 5694576
    Abstract: In an information processing system having a data processing apparatus, a control unit for a cache memory, and a storage unit for storing a record, respectively interconnected together, wherein when the control unit receives from the data processing apparatus a write request for a record to be written and if the record to be written is not being stored in the cache memory, the control unit receives a data to be written in the object record from the data processing apparatus and stores the received data in the cache memory. After notifying the data processing apparatus of a completion of a data write process, the control unit checks if the object record in which the data stored in the cache memory is being stored in the storage unit, if the object record is being stored in the storage unit, the data in the cache memory is written in the storage unit, and if not, the data in the cache memory is not written and such effect is notified to the data processing apparatus.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: December 2, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Shigeo Homma, Yoshihiro Asaka, Yoshiaki Kuwahara, Akira Kurano, Masafumi Nozawa, Hiroyuki Kitajima
  • Patent number: 5682396
    Abstract: A control unit in a storage subsystem connected to a central processing unit includes: a plurality of storage units for storing a plurality of record groups, each of which includes at least one data record and at least one parity record for recovering the contents of the data record, a cache memory; apparatus for receiving a write request issued by the central processing unit, the write request having write data to be written into one data record in the storage units; apparatus for storing the write data into the cache memory and reporting the completion of the write request to the central processing unit; apparatus for loading data of a data record and values of a parity record, each of the data of the data record and values of a parity record, each of the data of the data record and the values of the parity record being necessary for generation of updated values of a parity record of a record group including the one data record, from the storage units into the cache memory, after the reporting by the receiv
    Type: Grant
    Filed: January 29, 1992
    Date of Patent: October 28, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Hiroyuki Kitajima, Kouji Arai, Yoshihisa Kamo
  • Patent number: 5680574
    Abstract: The control unit arbitrarily selects a disk unit among the disk units that are inactive when the control unit receives an input/output request involving either read or staging. For a write request, the control unit selects a master disk unit in the disk unit group for the immediate writing of data, and a disk unit other than the above-mentioned master disk is preferably selected to execute the read and staging unit. After writing is used to write the data into the other disk units after the write request execution is completed by writing to the master disk unit.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: October 21, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 5638508
    Abstract: A data processing system for processing transactions, wherein a log record to be used for recovery of the system is written into a log file for system recovery in synchronism with the end of a transaction, and log records other than resident information are is written for a plurality of transactions into a log file for archives.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: June 10, 1997
    Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.
    Inventors: Sadasaburoh Kanai, Toshiaki Tsuboi, Hiroyuki Kitajima, Takashi Sumiyoshi
  • Patent number: 5623631
    Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: April 22, 1997
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.
    Inventors: Toshiaki Tsuboi, Akira Yamamoto, Shigeo Honma, Yoshihiro Asaka, Koji Ozawa, Hiroyuki Kitajima, Michio Miyazaki
  • Patent number: 5606684
    Abstract: A buffer memory capable of storing contents of a plurality of tracks of a disk volume is provided in a disk controller or a disk drive, and in dump processing requested by a higher rank unit (CPU) to the disk controller, the data is immediately transferred from the buffer memory if the data to be dumped is present in the buffer memory, and if the data to be dumped is not present in the buffer memory, dump prefetching into the buffer memory is started and the execution of the dump processing is interrupted so that an on-line input/output operation other than the dump processing is accepted. When the dump prefetching into the buffer memory is over, the interrupted dump processing is resumed.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: February 25, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Nakano, Masafumi Nozawa, Kiyoshi Hisano, Akihito Ogino, Akira Kurano, Hiroyuki Kitajima, Akihiko Togawa
  • Patent number: 5497472
    Abstract: In an information processing system having a data processing apparatus, a control unit for a cache memory, and a storage unit for storing a record, respectively interconnected together, wherein when the control unit receives from the data processing apparatus a write request for a record to be written and if the record to be written is not being stored in the cache memory, the control unit receives a data to be written in the object record from the data processing apparatus and stores the received data in the cache memory. After notifying the data processing apparatus of a completion of a data write process, the control unit checks if the object record in which the data stored in the cache memory is being stored in the storage unit, if the object record is being stored in the storage unit, the data in the cache memory is written in the storage unit, and if not, the data in the cache memory is not written and such effect is notified to the data processing apparatus.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: March 5, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Shigeo Homma, Yoshihiro Asaka, Yoshiaki Kuwahara, Akira Kurano, Masafumi Nozawa, Hiroyuki Kitajima
  • Patent number: 5418929
    Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: May 23, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Tsuboi, Akira Yamamoto, Shigeo Honma, Yoshihiro Asaka, Koji Ozawa, Hiroyuki Kitajima, Michio Miyazaki
  • Patent number: 5410666
    Abstract: A buffer memory capable of storing contents of a plurality of tracks of a disk volume is provided in a disk controller or a disk drive, and in dump processing requested by a higher rank unit (CPU) to the disk controller, the data is immediately transferred from the buffer memory if the data to be dumped is present in the buffer memory, and if the data to be dumped is not present in the buffer memory, dump prefetching into the buffer memory is started and the execution of the dump processing is interrupted so that an on-line input/output operation other than the dump processing is accepted. When the dump prefetching into the buffer memory is over, the interrupted dump processing is resumed.
    Type: Grant
    Filed: September 17, 1990
    Date of Patent: April 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Nakano, Masafumi Nozawa, Kiyoshi Hisano, Akihito Ogino, Akira Kurano, Hiroyuki Kitajima, Akihiko Togawa
  • Patent number: 5388016
    Abstract: A magnetic tape data management method and apparatus is described that reduces the access time for updating and referring to directory data. At the time of accessing data on a magnetic tape loaded in a magnetic tape subsystem, directory data for the magnetic tape is, in response to the completion of the processing of data, recorded in a region located near the place at which the magnetic tape head is positioned at that time, said region constituting a directory data region (DDR). Further, a directory data memory for recording directory data from the magnetic tape is provided in the magnetic tape subsystem, remote from the tape. At the time of accessing data on the magnetic tape loaded in the magnetic tape subsystem, directory data for the magnetic tape processing is, in response to completion of the processing of data, recorded in the directory data memory in the magnetic tape subsystem.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: February 7, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Sadasaburoh Kanai, Hiroyuki Kitajima, Toshifumi Nishimura, Katsuharu Kakuse, Minoru Kosuge
  • Patent number: 5307473
    Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.
    Type: Grant
    Filed: February 10, 1992
    Date of Patent: April 26, 1994
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.
    Inventors: Toshiaki Tsuboi, Akira Yamamoto, Shigeo Honma, Yoshihiro Asaka, Koji Ozawa, Hiroyuki Kitajima, Michio Miyazaki
  • Patent number: 5261065
    Abstract: With respect to input/output requests; a microprogram controls collection of data according to the data format; data accessing divides the requests for every recording medium and performs asynchronous processing; an on-line process is carried out in view of the processing priority order of the requests; parallel accessing sets requests for each medium; buffer control assures a block buffer and a page address list before receiving requests; data accessing sets a list of CCHHR codes in response to a continuous characteristic of the stored state in the recording medium; and mode deciding judges the two data transfer modes, a page search mode and a data search mode, in response to the requests.
    Type: Grant
    Filed: March 9, 1990
    Date of Patent: November 9, 1993
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Shoo Urabe, Masashi Tsuchida, Hideo Mutoh, Yukio Nakano, Toshio Honma, Kiyoshi Yata, Hiroyuki Kitajima, Tadashi Ohsone, Nobuhiro Taniquchi
  • Patent number: 5257352
    Abstract: An input/output control apparatus connected to a plurality of input/output units such as disc systems and an input/output control method. A cache memory is divided into a plurality of storage areas for data management. Data stored in the disc systems are stored in the storage areas. In response to an output request from a HOST system to the disc systems, data outputted from the latter are stored in the storage areas of the cache memory. The data stored in the storage areas and outputted therefrom in response to the output request are transferred to the disc systems. The storage areas storing the data requested and not yet stored in the disc systems are grouped correspondingly to the disc systems where the output data are to be stored. The resulting group is managed as a first attribute group. Write-after processing for every disc units can be executed in parallel efficiently without involving high processing overhead.
    Type: Grant
    Filed: July 5, 1990
    Date of Patent: October 26, 1993
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Akira Yamamoto, Toshiaki Tsuboi, Takao Sato, Yoshihiro Asaka, Shigeo Honma, Shigeru Kishiro, Michio Miyazaki, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 5253351
    Abstract: In a control unit having a external storage device, a method for selecting a loading method of data stored in the cache memory into the cache memory in accordance with an access pattern to the data, and an apparatus therefor are disclosed. The selection of the loading method is selection of control mode or procedure in accordance with the loading method, and it is attained by a learn function.
    Type: Grant
    Filed: August 8, 1989
    Date of Patent: October 12, 1993
    Assignees: Hitachi, Ltd., Microcomputer Engineering Ltd.
    Inventors: Akira Yamamoto, Toshiaki Tsuboi, Shigeo Honma, Hiroyuki Kitajima, Akira Kurano, Masafumi Nozawa, Katsunori Nakamura, Kosaku Kambayashi, Toshio Nakano, Yoshiro Shiroyanagi
  • Patent number: 5239644
    Abstract: A controller with a buffer is provided between a main memory and an external storage. This controller supplies a given request for access to the external storage and issues a preload request for a retrieval extent of the next access request by the time when data associated with this first access request is completely transferred to the buffer memory or to the main memory. Moreover, the controller stores the preloaded data in the buffer and, for the next access request, it transfers the data stored in the buffer to the main memory. Therefore, even when the host side (CPU) is processing, the access to the external storage can be made simultaneously, thus the response time and the operating ratio of the computer system being improved.
    Type: Grant
    Filed: September 9, 1991
    Date of Patent: August 24, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takaaki Seki, Hiroyuki Kitajima, Tadashi Ohsone, Hirofumi Nakagawa
  • Patent number: 5193154
    Abstract: A buffered peripheral system comprises a backup memory and a primary control unit which has a buffer memory for temporarily storing a copy of the contents of a buffer memory which stores data to be written to a peripheral device and a control device for issuing a command necessary to write the block stored in the buffer memory device to the peripheral device. The primary control unit also includes a recording device for recording the block number corresponding to the block which was most recently written to the peripheral device. The blocks of data which have been written to the peripheral device is then deleted from the backup memory to make room for storing further blocks of data. The system further has a backup control unit substantially identical to the primary control unit. Only the primary control unit normally operates to control the writing to the peripheral device.
    Type: Grant
    Filed: October 25, 1991
    Date of Patent: March 9, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Kitajima, Akira Yamamoto, Takashi Doi, Masafumi Nozawa