Patents by Inventor Hiroyuki Kitamura
Hiroyuki Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210199538Abstract: An on-road driving test system includes a determination condition storing unit, a vehicle speed storing unit, a predicted vehicle speed distribution calculating unit, and a determining unit. The determination condition storing unit stores a determination condition including at least a vehicle speed distribution condition for determining whether an on-road driving test is valid. The vehicle speed storing unit stores an actual measured vehicle speed actually measured at each geographical point by one or more vehicles. The predicted vehicle speed distribution calculating unit calculates a predicted vehicle speed distribution based on the actual measured vehicle speed, the predicted vehicle speed distribution being a vehicle speed distribution predicted to be obtained if a vehicle is driven on a set driving route. The determining unit determines whether the predicted vehicle speed distribution satisfies the vehicle speed distribution condition.Type: ApplicationFiled: May 17, 2019Publication date: July 1, 2021Applicant: HORIBA, LTD.Inventors: Nobutaka KIHARA, Hiroyuki KITAMURA, Toshiyuki MICHIKITA, Sayaka YOSHIMURA
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Patent number: 9159286Abstract: The present invention includes, in addition to transistors each (Mm,n) provided at the intersection of a gate bus line (GLn) with a data bus line (DLm): block potential applying transistors (DMn) connected to respective ends of gate bus lines (GLn) which ends are not connected to a gate driver (11); a potential supply line (VLL) connected to the gate bus lines (GLn) via the block potential applying transistors (DMn); and a blocking signal supplying section (131) for, immediately after the gate driver (11) supplies a first conduction signal for bringing the transistors (Mm,n) into conduction, supplying to the block potential applying transistors (DMn), a second conduction signal for bringing the block potential applying transistors (DMn) into conduction.Type: GrantFiled: October 28, 2010Date of Patent: October 13, 2015Assignee: Sharp Kabushiki KaishaInventors: Hiromi Enomoto, Shinsuke Yokonuma, Yoji Inui, Toshihiko Miyashita, Hiroyuki Kitamura
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Publication number: 20120262363Abstract: The present invention includes, in addition to transistors each (Mm,n) provided at the intersection of a gate bus line (GLn) with a data bus line (DLm): block potential applying transistors (DMn) connected to respective ends of gate bus lines (GLn) which ends are not connected to a gate driver (11); a potential supply line (VLL) connected to the gate bus lines (GLn) via the block potential applying transistors (DMn); and a blocking signal supplying section (131) for, immediately after the gate driver (11) supplies a first conduction signal for bringing the transistors (Mm,n) into conduction, supplying to the block potential applying transistors (DMn), a second conduction signal for bringing the block potential applying transistors (DMn) into conduction.Type: ApplicationFiled: October 28, 2010Publication date: October 18, 2012Applicant: Sharp Kabushiki KaishaInventors: Hiromi Enomoto, Shinsuke Yokonuma, Yoji Inui, Toshihiko Miyashita, Hiroyuki Kitamura
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Publication number: 20110281411Abstract: An amorphous silicon layer and a single crystal silicon layer are formed in an upper portion of a silicon pillar. Then, by performing the selective epitaxial growth method twice, an amorphous silicon layer and an amorphous silicon germanium layer are formed in this order on the silicon pillar. Subsequently, by heat treatment, a second impurity diffusion layer including a single crystal silicon layer is formed in the upper portion of the silicon pillar. At the same time of the formation of the second impurity diffusion layer, a first contact plug including a single crystal silicon layer and a polycrystalline silicon germanium layer is formed on the silicon pillar. Then, a second contact plug made of metal is formed so that it is connected to the first contact plug.Type: ApplicationFiled: May 9, 2011Publication date: November 17, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Hiroyuki KITAMURA
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Patent number: 7767513Abstract: A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that covers at least the gate insulating film and the side portions of the gate electrode, in which the silicon nitride film is formed by laminating a plurality of silicon nitride layers by repeating a step of forming a silicon nitride layer of a predetermined thickness by the low-pressure chemical vapor deposition method and a step of exposing the silicon nitride layer to nitrogen.Type: GrantFiled: March 18, 2008Date of Patent: August 3, 2010Assignee: Elpida Memory, Inc.Inventor: Hiroyuki Kitamura
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Patent number: 7491652Abstract: A process for manufacturing semiconductor devices in an in-line processing includes the steps of: forming a silicon nitride film on a semiconductor wafer by nitrization in a reactor chamber having an inner pressure at a specific pressure; reducing the inner pressure from the specific pressure; raising the inner pressure up to the specific pressure; replacing the semiconductor wafer with another semiconductor wafer; and forming a nitride film on the another semiconductor wafer at the specific pressure.Type: GrantFiled: June 26, 2006Date of Patent: February 17, 2009Assignee: Elpida Memory, Inc.Inventors: Naonori Fujiwara, Hiroyuki Kitamura
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Publication number: 20080272444Abstract: A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that covers at least the gate insulating film and the side portions of the gate electrode, in which the silicon nitride film is formed by laminating a plurality of silicon nitride layers by repeating a step of forming a silicon nitride layer of a predetermined thickness by the low-pressure chemical vapor deposition method and a step of exposing the silicon nitride layer to nitrogen.Type: ApplicationFiled: March 18, 2008Publication date: November 6, 2008Applicant: Elpida Memory, Inc.Inventor: Hiroyuki KITAMURA
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Publication number: 20080237912Abstract: In a method of producing a stamper for roughening a substrate of an optical recording medium, a masking treatment is carried out prior to a blasting treatment, whereby a second pit forming site of a metal plate is protected such that the second pit forming site is not broken in the following blasting treatment. A mask of an adhesive sheet is attached to the second pit forming site in the masking treatment, and then a part of one major surface of the metal plate, exposed between the mask, is roughened in the blasting treatment. An original stamper of the metal plate, having a partly roughened major surface, is obtained by the blasting treatment.Type: ApplicationFiled: March 28, 2008Publication date: October 2, 2008Applicant: FUJIFILM CorporationInventors: Yanlong Che, Hiroyuki Kitamura, Michihiro Shibata
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Publication number: 20080130169Abstract: According to one embodiment, a disk device includes a recording medium, a spindle motor which supports and rotates the recording medium, a head, and a head actuator which supports the head for movement. The spindle motor includes a rotor, a fluid bearing which supports the rotor for rotation, a cylindrical magnet coaxially fixed to the rotor, an annular stator located outside the rotor in the circumferential direction, and a magnetic shielding member which blocks leakage flux from a magnetic circuit. The magnetic shielding member has an annular portion which extends at right angles to an axis of rotation of the rotor and covers an upper surface portion of the stator, and a cylindrical portion which extends along the axis of rotation of the rotor and radially faces the whole outer peripheral surface of the rotor except a region where the stator and the magnet face each other.Type: ApplicationFiled: November 28, 2007Publication date: June 5, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Kitamura
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Publication number: 20080090375Abstract: A process for forming a capacitor in a semiconductor device includes the step of forming a two-layer capacitor insulation film including a silicon oxynitride film and a tantalum oxide film. The step for forming the silicon oxynitride film is performed at a first substrate temperature, and the step of forming the tantalum oxide film uses a heat treatment performed at a second substrate temperature. The second substrate temperature is lower than the maximum of the first substrate temperature, to provide a higher capacitance per unit area and a lower leakage current in the capacitor.Type: ApplicationFiled: October 17, 2007Publication date: April 17, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Hiroyuki KITAMURA
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Patent number: 7298002Abstract: A semiconductor device includes cylindrical capacitors each including corresponding cylindrical electrodes. Each cylindrical electrode includes hemispherical silicon grains. The hemispherical silicon grains protruding from an upper region of the cylindrical electrode have a large size, and the hemispherical silicon grains protruding from a lower region of the cylindrical electrode have a small size or the lower region of the cylindrical electrode has no hemispherical silicon grains.Type: GrantFiled: June 24, 2005Date of Patent: November 20, 2007Assignee: Elpida Memory Inc.Inventors: Hiroyuki Kitamura, Yuki Togashi, Hiroyasu Kitajima, Noriaki Ikeda, Yoshitaka Nakamura, Eiichiro Kakehashi
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Publication number: 20070210365Abstract: A semiconductor device includes a cylindrical capacitor. A size of hemispherical silicon grains (HSGs) formed in a straight portion of the cylindrical capacitor is smaller than a size of HSGs formed in a bowing portion of the cylindrical capacitor.Type: ApplicationFiled: February 27, 2007Publication date: September 13, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Yuki TOGASHI, Hiroyuki KITAMURA
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Patent number: 7242473Abstract: An data processing system 4 includes: an integral part 43 which integrates, by two mutually different times, light intensities indicating light intensity signals outputted from light detectors 24 respectively provided for detecting intensities of scattered light and transmitted light generated by irradiating a sample powder S with light and then outputs each of the integrated values; an actuator control part 44 which generates and outputs a control signal for a vibration actuator 32 which drops the sample powder S stored in a sample housing so that one of the integrated values of light intensity outputted from the integral part 43 becomes closer to a set value previously defined; and a particle size distribution calculation part 45 which calculates the particle size distribution of the sample powder S based on another of the integrated values of light intensity outputted from the integral part 43.Type: GrantFiled: August 25, 2006Date of Patent: July 10, 2007Assignee: Horiba, Ltd.Inventors: Yoshiaki Togawa, Hiroyuki Kitamura, Takeshi Shimizu
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Publication number: 20070046937Abstract: An data processing system 4 includes: an integral part 43 which integrates, by two mutually different times, light intensities indicating light intensity signals outputted from light detectors 24 respectively provided for detecting intensities of scattered light and transmitted light generated by irradiating a sample powder S with light and then outputs each of the integrated values; an actuator control part 44 which generates and outputs a control signal for a vibration actuator 32 which drops the sample powder S stored in a sample housing so that one of the integrated values of light intensity outputted from the integral part 43 becomes closer to a set value previously defined; and a particle size distribution calculation part 45 which calculates the particle size distribution of the sample powder S based on another of the integrated values of light intensity outputted from the integral part 43.Type: ApplicationFiled: August 25, 2006Publication date: March 1, 2007Inventors: Yoshiaki Togawa, Hiroyuki Kitamura, Takeshi Shimizu
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Publication number: 20070004223Abstract: A process for manufacturing semiconductor devices in an in-line processing includes the steps of: forming a silicon nitride film on a semiconductor wafer by nitrization in a reactor chamber having an inner pressure at a specific pressure; reducing the inner pressure from the specific pressure; raising the inner pressure up to the specific pressure; replacing the semiconductor wafer with another semiconductor wafer; and forming a nitride film on the another semiconductor wafer at the specific pressure.Type: ApplicationFiled: June 26, 2006Publication date: January 4, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Naonori Fujiwara, Hiroyuki Kitamura
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Patent number: 7042557Abstract: A dry particle-size distribution measuring apparatus and method is provided for suspending a plurality of bristle members across a support surface of a dispensing trough with bristles being arranged to contact and disperse any clusters of particles to a primary state prior to releasing the particles to a sample flow cell. A source of light can irradiate the sample flow cell and a detector unit can measure any scattered and/or diffracted light to provide corresponding signals. A control unit can determine the size and distribution of particles from the corresponding signals. The bristle members can be mounted on a brush unit that is directly mounted on the trough and both the trough and the brush unit can be driven by the same vibrator unit.Type: GrantFiled: December 18, 2002Date of Patent: May 9, 2006Assignee: Horiba, Ltd.Inventors: Tetsuji Yamaguchi, Hiroyuki Kitamura
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Publication number: 20060048374Abstract: In disk cartridge production, in order to enhance adhesion between a disk-shaped center hub provided with a center hole and a tacky ring formed of ring-shaped double sided adhesive tape material, when the tacky ring adhered on a base film is attached to a lower surface of the center hub before attaching the center hub to a central portion of a disk via the tacky ring, the base film is supported from the rear side by an elastic ring pad. The elastic ring pad has an outer diameter which is smaller than the outer diameter of the center hub but larger than the outer diameter of the tacky ring and an inner diameter which is larger than the inner diameter of the center hole of the center hub but smaller than the inner diameter of the tacky ring.Type: ApplicationFiled: September 1, 2005Publication date: March 9, 2006Inventors: Akira Mizuta, Hiroyuki Kitamura
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Publication number: 20060022251Abstract: A semiconductor device includes cylindrical capacitors each including corresponding cylindrical electrodes. Each cylindrical electrode includes hemispherical silicon grains. The hemispherical silicon grains protruding from an upper region of the cylindrical electrode have a large size, and the hemispherical silicon grains protruding from a lower region of the cylindrical electrode have a small size or the lower region of the cylindrical electrode has no hemispherical silicon grains.Type: ApplicationFiled: June 24, 2005Publication date: February 2, 2006Inventors: Hiroyuki Kitamura, Yuki Togashi, Hiroyasu Kitajima, Noriaki Ikeda, Yoshitaka Nakamura, Eiichiro Kakehashi
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Patent number: 6939760Abstract: There is provided a method for manufacturing a semiconductor device including a capacitor having a lower electrode, an upper electrode and a capacitive insulating film between the lower electrode and the upper electrode on a semiconductor substrate, wherein the capacitive insulating film is formed on the lower electrode over the semiconductor substrate using a chemical vapor deposition method, the method including: a lower electrode forming step of forming the lower electrode on the semiconductor, a dual-stage deposition step including a first stage for introducing a material gas containing a specified metal into a reactor in which the semiconductor substrate is placed and a second stage for subsequently introducing an oxidizing gas into the reactor, and wherein a metal oxide film as an oxide of the specified metal is formed on the lower electrode over the semiconductor substrate, by repeating the dual-stage deposition step two or more times, thereby forming the capacitive insulating film; and an upper electrType: GrantFiled: July 1, 2003Date of Patent: September 6, 2005Assignee: Elpida Memory, Inc.Inventors: Hirofumi Fujioka, Kenichi Koyanagi, Hiroyuki Kitamura
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Publication number: 20050141136Abstract: A spindle motor includes a fixed shaft, a rotating sleeve, and an outer ring member. The rotating sleeve has an inner peripheral surface opposed to an outer peripheral surface of the fixed shaft across a first fine gap, an outer peripheral surface, and a bottom surface. The outer ring member has an opposite surface opposed to the bottom surface of the rotating sleeve across a second fine gap and an inner peripheral surface opposed to the outer peripheral surface of the rotating sleeve across a third fine gap and is provided fixedly. The first, second, and third fine gaps are filled with a dynamic pressure generating fluid. A first radial dynamic pressure generating portion is located singly in the first fine gap, and a second radial dynamic pressure generating portion in the third fine gap. A thrust dynamic pressure generating portion is located in the second fine gap.Type: ApplicationFiled: December 23, 2004Publication date: June 30, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Kitamura