Abstract: A redundant address memory circuit is used in a memory element exchange circuit associated to a memory matrix composed of FAMOS memory cells and provided with a redundant memory array composed of FAMOS memory cells. The redundant address memory circuit comprises a FAMOS memory cell for storing a defective address, and an output circuit connected to the defective address storing FAMOS memory cell for generating an output signal corresponding to the content of the defective address storing FAMOS memory cell. In addition, there is provided a circuit connected to the defective address storing FAMOS memory cell and to the output circuit for receiving the content of the defective address storing FAMOS memory cell through the output circuit so as to write the content of the defective address storing FAMOS memory cell into the defective address storing FAMOS memory cell when a new data is written to the memory matrix.

Abstract: A semiconductor memory in which each of memory cells includes a memory transistor having a control gate connected to a word line, a floating gate and a drain-source path connected to a bit line, is disclosed. In a data programming operation mode, a programming voltage is applied via the word and bit lines to the control gate and the drain-source path of the memory transistor to inject carriers into the floating gate thereof. In order to detect whether or not the memory transistor is well programmed, a program verifying operation is carried out successively. To this end, the bit line is discharged to the low level and the word line is then supplied with a reading-out voltage. If the data programming is insufficient, the memory transistor is turned ON by the reading-out voltage, so that the bit line is held at a level near the low level. On the other hand, in case where the memory transistor is well programmed, it is not turned ON by the reading-out, so that the bit line is charged.

Abstract: A non-volatile semiconductor memory device has a plurality of memory cells which are coupled to a plurality of row or column lines through which a high voltage is supplied in a data write operation and a plurality of switching circuits, each of which is coupled to the corresponding row or column line. In a data write operation, only one of switching circuits is turned on to supply the high voltage to only one row or column lines coupled to a memory cell in which a data is to be written.

Abstract: An input circuit incorporated in a semiconductor device is provided in association with a multi-purpose input terminal which is shared by first and second input signals different in voltage level from each other, and the input circuit comprises an input buffer circuit for storing the first input signal, a series combination of a first field effect transistor, an intermediate node and a second field effect transistor coupled between the multi-purpose input terminal and an internal circuit supplied with the second input signal, a resistor coupled between a source of constant voltage and the intermediate node, a first control circuit producing a first gate control signal supplied to a gate electrode of the second field effect transistor, and a second control circuit capable of detecting the second input signal and producing a second gate control signal supplied to a gate electrode of the first field effect transistor, so that the second field effect transistor keeps off even if the first field effect transistor

Abstract: A control circuit provided in association with a multi-purpose input node is provided with an input signal detecting circuit for relaying a middle voltage level from the multipurpose input node to the internal circuit, a charge-pump circuit activated in the presence of a high voltage level for producing an extremely high voltage level, a transferring circuit coupled between the multipurpose input node and the charge-pump circuit, and a gate transistor coupled between the multipurpose input node and the output node, and the extremely high voltage level is supplied to not only the gate transistor but also the transferring circuit, so that the high voltage level is fully transferred to the charge-pump circuit, thereby allowing the gate transistor to transfer the high voltage level to the output node without any reduction in voltage level.

Abstract: For precise read-out operation at an improved speed, there is disclosed a semiconductor memory device fabricated on a semiconductor substrate of a first conductivity type and including a plurality of memory cells, each memory cell comprising (a) an insulating film covering a surface portion of the semiconductor substrate, (b) a gate electrode formed on the insulating film and located over a channel forming region in the surface portion of the semiconductor substrate, a channel being produced in the channel forming region when the memory cell is selected, (c) a first impurity region having a second conductivity type opposite to the first conductivity type and formed in the surface portion of the semiconductor substrate, the first impurity region being contiguous to the channel forming region or spaced apart from the channel forming region depending upon a bit of information stored therein, and (d) a second impurity region of the second conductivity type formed in the surface portion of the semiconductor substr

Abstract: For improvement of operation speed, a sense amplifier circuit comprising (a) a signal input node, (b) a signal output node, (c) load means with a relatively large resistance provided between a source of voltage and the signal output node, (d) a first field effect transistor with a relatively small channel resistance provided between the signal input node and the signal output node and having a gate electrode, (e) a logic gate having at least one input node connected to the signal input node and an output node connected to the gate electrode of the first field effect transistor, and (f) a second field effect transistor with a relatively small channel resistance provided between the source of voltage and the signal output node and having a gate electrode connected to the output node of the logic gate.

Abstract: A circuit for detecting the level of an input voltage is disclosed, in which the input voltage is converted into a current and this current is compared with a reference current obtained by converting a reference voltage. To accomplish such circuit functions, this level detection circuit comprises means for converting the input voltage into a first current, means for converting the reference voltage into a second current, means for producing a third current relative to the first current, means for producing a fourth current relative to the second current, and means for combining the third and fourth current. A detection output terminal is coupled to the combining means.