Patents by Inventor Hiroyuki Kogata

Hiroyuki Kogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8194561
    Abstract: A packet relay device receives an input packet via a first communication port out of a plurality of communication ports of the packet relay device and transmits the input packet via a second communication port out of the plurality of communication ports. The packet relay device includes a learning table storage, a header adder, a discard determiner, and a packet reducer. The learning table storage stores a source address contained in the input packet, in association with an input port identifier capable of identifying the first communication port. The header adder adds an internal transfer header containing the input port identifier to the input packet to generate an internal transfer packet. The discard determiner determines whether to discard the internal transfer packet. The packet reducer reduces the internal transfer packet to preserve at least the source address and the input port identifier upon determining to discard the internal transfer packet.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: June 5, 2012
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Kogata, Akio Shinohara
  • Patent number: 8149856
    Abstract: Each of the plurality of queues stores packet data of a received packet. The read concession assignor assigns one of the plurality of queues with a read concession for a predefined time period. The overdraft storage stores an overdraft amount in connection with each of the plurality of queues. The read adequacy determiner determines, in accordance with an overdraft amount stored in connection with one queue out of the plurality of queues, whether to read packet data from the one queue. The overdraft updater updates at least one of a first overdraft amount stored in connection with a first queue and a second overdraft amount stored in connection with a second queue different from the first queue upon reading packet data from the first queue during a time period while the second queue is assigned with the read concession.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: April 3, 2012
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Kogata, Hisaya Ogasawara, Akio Shinohara
  • Publication number: 20100014539
    Abstract: Each of the plurality of queues stores packet data of a received packet. The read concession assignor assigns one of the plurality of queues with a read concession for a predefined time period. The overdraft storage stores an overdraft amount in connection with each of the plurality of queues. The read adequacy determiner determines, in accordance with an overdraft amount stored in connection with one queue out of the plurality of queues, whether to read packet data from the one queue. The overdraft updater updates at least one of a first overdraft amount stored in connection with a first queue and a second overdraft amount stored in connection with a second queue different from the first queue upon reading packet data from the first queue during a time period while the second queue is assigned with the read concession.
    Type: Application
    Filed: September 24, 2009
    Publication date: January 21, 2010
    Applicant: Fujitsu Limited
    Inventors: Hiroyuki KOGATA, Hisaya OGASAWARA, Akio SHINOHARA
  • Publication number: 20100002703
    Abstract: A packet relay device receives an input packet via a first communication port out of a plurality of communication ports of the packet relay device and transmits the input packet via a second communication port out of the plurality of communication ports. The packet relay device includes a learning table storage, a header adder, a discard determiner, and a packet reducer. The learning table storage stores a source address contained in the input packet, in association with an input port identifier capable of identifying the first communication port. The header adder adds an internal transfer header containing the input port identifier to the input packet to generate an internal transfer packet. The discard determiner determines whether to discard the internal transfer packet. The packet reducer reduces the internal transfer packet to preserve at least the source address and the input port identifier upon determining to discard the internal transfer packet.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 7, 2010
    Inventors: Hiroyuki Kogata, Akio Shinohara
  • Patent number: 6611523
    Abstract: An ATM cell multiplexer is arranged so that in the up direction from the terminal equipment to the ATM switchboard cells from a cell terminal portion in CLAD units are held in a cell holding portion through a Utopia Level 2 interface under the control of a communication controller in the CLAD units, and an ATM bus scheduler makes the cell holding portion transmit the cells to an ATM bus by assigning a transmission right for every cell holding portion of the CLAD units in accordance with a preset schedule table based on at least one of predetermined service categories and a traffic control corresponding to a traffic quantity, while in the down direction from the ATM switchboard to the terminal equipment the cells are broadcast from the ATM bus to the cell holding portion of each CLAD unit for a cell transfer and the communication controller makes the cell holding portion transfer the cells to the cell terminal portion through the Utopia Level 2 interface to decide whether or not the cells are addressed to itse
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: August 26, 2003
    Assignee: Fujitsu Limited
    Inventors: Yasuo Tanaka, Hiroyuki Kogata
  • Publication number: 20020172204
    Abstract: An ATM cell multiplexer is arranged so that in the up direction from the terminal equipment to the ATM switchboard cells from a cell terminal portion in CLAD units are held in a cell holding portion through a Utopia Level 2 under the control of a communication controller in the CLAD units, and an ATM bus scheduler makes the cell holding portion transmit the cells to an ATM bus by assigning a transmission right for every cell holding portion of the CLAD units in accordance with a preset schedule table based on at least one of predetermined service categories and a traffic control corresponding to a traffic quantity, while in the down direction from the ATM switchboard to the terminal equipment the cells are broadcast from the ATM bus to the cell holding portion of each CLAD unit for a cell transfer and the communication controller makes the cell holding portion transfer the cells to the cell terminal portion through the Utopia Level 2 to decide whether or not the cells are addressed to itself.
    Type: Application
    Filed: January 6, 1999
    Publication date: November 21, 2002
    Inventors: YASUO TANAKA, HIROYUKI KOGATA