Abstract: This invention provides a kit or device for detection of prostate cancer and a method for detecting prostate cancer. This invention provides a kit or device for detection of prostate cancer comprising a nucleic acid capable of specifically binding to an miRNA in a sample from a subject or a complementary strand thereof and a method for detecting prostate cancer comprising measuring the miRNA in vitro.

Abstract: A semiconductor device includes a support member having first and second major surfaces and an elongate hole extending between the first and second major surfaces. The hole has first and second elongate edges extending along a side of the support member and opposed to each other. A plurality of first and second external connection terminals is provided along each of the first and second edges. The first and second external connection terminals each have one end located above the second major surface of the support member. A semiconductor chip is provided on the first major surface of the support member. The semiconductor chip includes connection pads arranged along the hole. The connection pads are electrically connected to the other ends of the first and second external connection terminals by first and second connection wires, respectively. The hole is filled with an insulation material.

Abstract: There is disclosed a three-dimensional semiconductor device having a printed wiring board or insulating film having first and second surfaces. Semiconductor components are packed on the first surface. External terminals are mounted to the second surface. Semiconductor components or a thin-film inductor producing a large amount of heat are installed in a space on the second surface via an anisotropic conductive film. This reduces the packaging density. After packaging, the rigidity of the printed wiring board or insulating film is enhanced. Heat generated by the semiconductor components is efficiently dissipated to reduce the affects on other components.

Abstract: In an evaluation tool for use in evaluating an LSI, a piezo-diffusion-resistor unit and a temperature monitor unit are disposed close to each other in a first layer, for example, near a corner area and a central area on an Si substrate. A polysilicon resistor array is disposed on that area of the Si substrate which excludes locations where the piezo-diffusion-resistor unit and temperature monitor unit are disposed. Over these elements, an Al wiring layer, or a second layer, is provided with an interlayer insulation film interposed. Thus, the evaluation tool is provided with a stepped structure which is substantially similar to a structure of an actual LSI product.

Abstract: A semiconductor device includes a support member having first and second major surfaces and an elongate hole extending between the first and second major surfaces. The hole has first and second elongate edges extending along a side of the support member and opposed to each other. A plurality of first and second external connection terminals is provided along each of the first and second edges. The first and second external connection terminals each have one end located above the second major surface of the support member. A semiconductor chip is provided on the first major surface of the support member. The semiconductor chip includes connection pads arranged along the hole. The connection pads are electrically connected to the other ends of the first and second external connection terminals by first and second connection wires, respectively. The hole is filled with an insulation material.

Abstract: A semiconductor chip is secured on a die-pad which has been depressed. One end of a tie-bar is combined with the die-pad. One of a lead is connected to the semiconductor chip by, for example, a bonding wire. A molded resin block covers up the die-pad, semiconductor chip and lead, and has an upper surface, a lower surface and sides. The other end of the tie-bar and the other end of the lead are exposed at the lower surface of the resin block. The surfaces of the tie-bar and lead, which are exposed, lie in substantially the same plane as at least the lower surface of the resin block. The lower surface of the die-pad may be exposed at the upper surface of the resin block, and the lower surface of the die-pad, which is exposed outside the resin block, may be set in substantially the same plane as the upper surface of the resin block.

Abstract: A semiconductor device according to the present invention includes a wiring substrate having a chip mounting face on which a connected portion is formed, a semiconductor chip having an element forming face on which externally connecting terminals are formed, the externally connecting terminals being electrically connected to the connected portion, and a resin-sealed layer formed between the wiring substrate and the semiconductor chip so as to cover at least a periphery of the semiconductor chip. The wiring substrate has a through hole bored from the chip mounting face to an undersurface thereof. Part of the through hole is formed outside a chip mounting region of the wiring substrate.

Abstract: In a resin-sealed semiconductor device, a semiconductor chip is mounted to a bed having a greater surface than that of the semiconductor chip. A lead section is comprised of a plurality of leads having their forward end portions arranged at given intervals around the semiconductor chip over the bed. The respective lead is connected by the tie bar to the bed. The bed, semiconductor chip, tie bars and portions of the leads are resin-sealed in a mold in such a way that a given surface side of the bed is exposed to an outside.

Abstract: A semiconductor device comprises a multiple-terminal integrated circuit formed on a substrate. The integrated circuit is formed on the upper surface of the substrate and electrically connected to a plurality of external terminals arranged on an under surface of the substrate. Part of a sealing member is embedded in a plurality of through-holes. The through holes are provided in the substrate to be in the vicinity of the plurality of external terminals. The sealing member seals the upper surface of the substrate, with the integrated circuit formed thereon.

Abstract: The present invention is provided with a transfer-mold package wherein the surface of a heat sink on which a semiconductor chip dissipating a large amount of heat is formed (the surface does not contact the chip) is exposed from the sealing resin. In this package, a concave portion 16a is formed in the surface of the heat sink to a depth of about 0.1 mm within a range of about 1 mm from the periphery of the heat sink. The concave portion prevents the sealing resin from extending toward the surface of the heat sink at the time of transfer mold, with the result that a resin burr can be prevented from occurring on the periphery of the surface of the heat sink exposed from the sealing resin, and the flatness of the surface of the heat sink can be prevented from being degraded by the resin burr.

Abstract: A resin-sealed type semiconductor device has a bed holding a semiconductor element on one surface and is provided with a plurality of protrusions on another surface. A lead frame includes a plurality of outer leads formed integral with the corresponding one of a plurality of inner leads, a bed section, and hanging pins for supporting the bed section. Each of the plurality of inner leads is connected to the corresponding one of a plurality of electrode pads by one of bonding wires. The semiconductor element, bonding wires, inner leads, hanging pins, and bed are sealed with resin such that the one surface of the bed, on which the protrusions are formed, is exposed to the outside.

Abstract: A semiconductor device includes a chip, a chip mounting plate, a heat radiating plate, first and second bumps, a conducting path forming member and a package. The chip has a semiconductor element in its main surface, and the rear surface thereof is mounted on the chip mounting plate with conductive adhesive. The chip mounting plate includes an insulating plate on which projecting portions are provided at corner portions, and a metal layer for covering the surface on which the chip is mounted. The projecting portions are formed such that the bottom surfaces thereof and the main surface of the chip are located on the same plane when the chip is mounted. The chip mounting plate is fixed to the heat radiating plate with adhesive. A first conducting path is provided on one surface of the conducting path forming member and a second conductive path is formed within the conducting path forming member.

Abstract: A semiconductor device comprises a semiconductor substrate having an integrated circuit having a connection electrode on its surface. A substrate mount section, having at least one concave portion on its main surface, is formed to support the semiconductor substrate to be fixed thereto. A first conductive metallic layer is formed on the main surface of the substrate mount section including a surface of the concave portion. A plurality of leads are supported and fixed to a peripheral portion of the main surface of the substrate mount section such that their end portions are opposite to the semiconductor substrate. The end portion of each lead and the connection electrode of the main surface of the semiconductor substrate are connected by a bonding wire.

Abstract: The present invention relates to a semiconductor device which comprises a semiconductor chip mounting section having a through hole, a radiating plate attached to one surface of the semiconductor chip mounting section so as to cover the through hole of the semiconductor chip mounting section, a semiconductor chip mounting plate which is formed within the through hole and mounted on the radiating plate, a surface of the semiconductor chip mounting plate, which is opposite to another surface thereof mounted on the radiating plate, being plated with gold, and the semiconductor chip mounting plate having improved electrical insulation properties and high thermal conductivity, and a semiconductor chip formed within the through hole and attached to the semiconductor chip mounting plate by a conductive adhesive.

Abstract: The semiconductor device of the present invention includes a semiconductor substrate on which an integrated circuit equipped with a connection electrode is formed on its main surface. At the center of the main surface, a substrate mounting portion having a cavity portion in which the semiconductor substrate is contained, is provided. At the periphery of the main surface of the substrate mounting portion, a plurality of leads are arranged and fixed to the periphery of the semiconductor substrate mounted in the cavity portion so that ends of the leads oppose each other. The plurality of leads include leads selected as power source lines. The connection electrode of the main surface of the semiconductor substrate is electrically connected to one of the ends of the leads via a bonding wire. A cap for covering at least the semiconductor substrate, the bonding wire and the ends of the leads is adhered to the substrate mounting portion.

Abstract: A semiconductor chip is mounted on a chip-mounting section. A conduction path forming section having a plurality of conduction paths formed therein is placed around the chip-mounting section. A heat sinking board is bonded to the backsides of the chip-mounting section and the conduction path forming section. In the conduction path forming section, a second insulating layer is formed with notches, whereby the exposed area of conduction paths that are wire-bonded to the chip-mounting section is increased.

Abstract: A PGA package type semiconductor device comprises an insulating lower package, leads, an insulating upper package, conductive wires, lead pins, and at least one semiconductor chip. The leads to be supplied with a power source potential are formed on the lower package. The upper package having a semiconductor chip-mounting portion at a central portion thereof is fixed to the lower package with the leads interposed therebetween. In the upper package, the conductive wires are formed on the leads with an insulator interposed therebetween. The lead pins vertically project from a peripheral portion of the upper package, and are electrically connected to the conductive wires. At least one semiconductor chip is mounted on the chip-mounting portion of the upper package. The semiconductor chip is connected to the leads by a TAB tape, and connected to the conductive wires by a TAB tape or bonding wires.

Abstract: A resin encapsulation type semiconductor device is provided with first leads electrically connected to the signal terminals of a semiconductor element and plate-like conductor elements electrically connected to the power source terminals of the semiconductor element. The first leads and the plate-like conductor elements are arranged in parallel with each other to form a two-layer structure. The number of the leads of the semiconductor element of the invented semiconductor device is reduced from that of the leads of the conventional semiconductor device. At least one through hole is formed in each of the plate-like conductor elements in a power source lead frame so as to make the flow distribution more uniform than in the plate-like conductor elements without the through holes.

Abstract: There is provided a semiconductor device comprising a lead frame including an island and a plurality of leads, a semiconductor chip, mounted on the island, having bonding pads, the semiconductor chip further including circuit blocks connected to bonding pads, and an insulating circuit substrate, mounted on the island, including a plurality of conductive layers each having connection pads. In the structure, the bonding pads are connected to the connection pads to provide electrical connections among the circuit blocks.