Abstract: An active energy ray-curable lithographic printing ink including a rosin-modified resin (A), an active energy ray-curable compound (B), a photopolymerization initiator (C), and an extender pigment (D), where the active energy ray-curable compound (B) includes dipentaerythritol hexaacrylate (B1), and an amount of the dipentaerythritol hexaacrylate (B1) relative to a total mass of the active energy ray-curable lithographic printing ink is within a range from 20 to 37% by mass. The photopolymerization initiator (C) includes at least two types of compounds selected from acylphosphine oxide-based compounds (C1), thioxanthone-based compounds (C2), and oxime ester-based compounds (C3), an amount of the extender pigment (D) relative to a total mass of the active energy ray-curable lithographic printing ink is within a range from 0.1 to 10% by mass, and a viscosity of the ink at 25° C. is within a range from 10 to 120 Pa·s.

Abstract: A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

Abstract: A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

Abstract: A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

Abstract: A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

Abstract: A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition.

Abstract: A method of producing an ink cured product having a step of printing an active energy beam-curable ink comprising a monomer having an ethylenic double bond and a photopolymerization initiator onto a substrate, and then curing the active energy beam-curable ink with an active energy beam, wherein the monomer having an ethylenic double bond comprises an acrylate monomer having a molecular weight of 330 or less and containing 1 to 3 acryloyl groups, the photopolymerization initiator comprises three or more types of compounds selected from the group consisting of (A1) ?-aminoalkylphenone compounds, (A2) acylphosphine oxide compounds, (B1) thioxanthone compounds and (B2) benzophenone compounds, and the substrate is either a paper having a high degree of smoothness or a plastic film.

Abstract: A level shifter converts an input signal having an amplitude between a ground and a first power supply voltage into an output signal having an amplitude between the ground and a second power supply voltage. The level shifter includes an input unit, driven by the first power supply voltage, that raises a first pulse signal at a rise of the input signal and raises a second pulse signal having the same polarity as the first pulse signal at a fall of the input signal, and a level shift unit that converts a signal level of the first pulse signal into an amplitude level of the second power supply voltage, and converts a signal level of the second pulse signal into an amplitude level of the second power supply voltage.

Abstract: A level shifter converts an input signal having an amplitude between a ground and a first power supply voltage into an output signal having an amplitude between the ground and a second power supply voltage. The level shifter includes an input unit, driven by the first power supply voltage, that raises a first pulse signal at a rise of the input signal and raises a second pulse signal having the same polarity as the first pulse signal at a fall of the input signal, and a level shift unit that converts a signal level of the first pulse signal into an amplitude level of the second power supply voltage, and converts a signal level of the second pulse signal into an amplitude level of the second power supply voltage.

Abstract: A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level. Each of the first and second level shift circuits includes a first transistor of a first conductivity type having a gate receiving the first and second pulse signals respectively, a source connected to a ground, and a drain that outputs a level shifted pulse signal, and a second transistor of a second conductivity type having a gate connected to the first transistor gate, a drain connected to the first transistor drain, and a source connected to the power supply via a connected transistor group, the connected transistor group includes at least one of the second conductivity type transistors.

Abstract: A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level. Each of the first and second level shift circuits includes a first conductivity type transistor having its gate receiving the first and second pulse signals respectively, its source connected to a ground, and its drain outputs a level shifted pulse signal, and a first transistor of a second conductivity type having its gate connected to the gate of the transistor of the first conductivity type, its drain connected to the drain of the transistor of the first conductivity type, and its source connected to the power supply via a connected transistor group, and the connected transistor group includes at least one of the second conductivity type transistors.

Abstract: A level shifter is operated at high speed. An input unit 2 generates a first one-shot pulse signal at the rise of an input signal and a second one-shot pulse signal having the same polarity as the first one-shot pulse signal at the fall of the input signal, and eliminates the generated first and second one-shot pulse signals using an output signal. A level shift unit 3 includes a level shift circuit LS1 that converts the signal level of the first one-shot pulse signal and a level shift circuit LS2 that converts the signal level of the second one-shot pulse signal. An output unit 4 is driven corresponding to the first and second one-shot pulse signals whose levels have been shifted and generates the output signal. A hold unit 1 maintains the level of the generated output signal.

Abstract: A level shifter is operated at high speed. An input unit 2 generates a first one-shot pulse signal at the rise of an input signal and a second one-shot pulse signal having the same polarity as the first one-shot pulse signal at the fall of the input signal, and eliminates the generated first and second one-shot pulse signals using an output signal. A level shift unit 3 includes a level shift circuit LS1 that converts the signal level of the first one-shot pulse signal and a level shift circuit LS2 that converts the signal level of the second one-shot pulse signal. An output unit 4 is driven corresponding to the first and second one-shot pulse signals whose levels have been shifted and generates the output signal. A hold unit 1 maintains the level of the generated output signal.

Abstract: A comparator circuit includes a first and a second PMOS transistors having sources connected to a first power supply and drains connected to a first node, NMOS transistors having sources connected to a second power supply and drains connected to the first node, a third and a fourth PMOS transistors having sources connected to the first power supply and the drains connected to a second node, and a third and a fourth NMOS transistors having sources connected to the second power supply and drains connected to the second node. A reference voltage and a voltage of a signal to be compared against are applied to gates of the thirst and the third PMOS transistors, and gates of the first and the third NMOS transistors. A comparator unit 1 outputs a comparison result between voltage of the first and the second nodes.

Abstract: A CMOS buffer circuit includes (1) a first CMOS inverter having a first p-channel MOSFET, which has a first threshold value that becomes smaller as the temperature rises and which is rendered ON when a digital signal exceeds the first threshold value, and a first n-channel MOSFET, having a second threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the first p-channel MOSFET, when a digital signal exceeds the second threshold value; and (2) a second CMOS inverter having a second p-channel MOSFET, which has a third threshold value that becomes smaller as the temperature rises and which is rendered ON when the first inverted signal exceeds the third threshold value, and a second n-channel MOSFET, having a fourth threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the second p-channel MOSFET, when the first inverted signal exceeds the fourth threshold value.

Abstract: A CMOS buffer circuit includes (1) a first CMOS inverter having a first p-channel MOSFET, which has a first threshold value that becomes smaller as the temperature rises and which is rendered ON when a digital signal exceeds the first threshold value, and a first n-channel MOSFET, having a second threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the first p-channel MOSFET, when a digital signal exceeds the second threshold value; and (2) a second CMOS inverter having a second p-channel MOSFET, which has a third threshold value that becomes smaller as the temperature rises and which is rendered ON when the first inverted signal exceeds the third threshold value, and a second n-channel MOSFET, having a fourth threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the second p-channel MOSFET, when the first inverted signal exceeds the fourth threshold value.