Patents by Inventor Hiroyuki Kunishima

Hiroyuki Kunishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10527872
    Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki
  • Patent number: 10295743
    Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Patent number: 10151881
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Hiroyuki Kunishima
  • Publication number: 20180052338
    Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Inventors: Hiroyuki KUNISHIMA, Yasutaka NAKASHIBA, Masaru WAKABAYASHI, Shinichi WATANUKI
  • Patent number: 9835882
    Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki
  • Publication number: 20170307824
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Tatsuya USAMI, Keiji SAKAMOTO, Hiroyuki KUNISHIMA
  • Patent number: 9739943
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Grant
    Filed: March 12, 2016
    Date of Patent: August 22, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Hiroyuki Kunishima
  • Patent number: 9508662
    Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Publication number: 20160334573
    Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 17, 2016
    Inventors: Hiroyuki KUNISHIMA, Yasutaka NAKASHIBA, Masaru WAKABAYASHI, Shinichi WATANUKI
  • Patent number: 9478547
    Abstract: Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films).
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: October 25, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Masashige Moritoki, Toshiji Taiji, Youichi Yamamoto
  • Publication number: 20160293481
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Application
    Filed: March 12, 2016
    Publication date: October 6, 2016
    Inventors: Tatsuya USAMI, Keiji SAKAMOTO, Hiroyuki KUNISHIMA
  • Patent number: 9312327
    Abstract: A semiconductor device having a capacitor which includes a first electrode electrically coupled to a transistor and a second electrode separate from the first electrode and covered with an interlayer insulating film, in which a plurality of coupling holes are formed in the interlayer insulating film and are in contact with the second electrode at the lower ends; and, when the capacitance of the second electrode is represented by C [nF] and the total area of the lower ends of the coupling holes is represented by A [?m2], the following expression (1) is satisfied. C/A?1.98 [nF/?m2]??(1) The elution of the second electrode constituting the capacitor at the lower ends of the coupling holes is suppressed.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 12, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ken Ozawa, Hiroyuki Kunishima
  • Publication number: 20160056115
    Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 25, 2016
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Publication number: 20160054521
    Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 25, 2016
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Publication number: 20150380480
    Abstract: A semiconductor device having a capacitor which includes a first electrode electrically coupled to a transistor and a second electrode separate from the first electrode and covered with an interlayer insulating film, in which a plurality of coupling holes are formed in the interlayer insulating film and are in contact with the second electrode at the lower ends; and, when the capacitance of the second electrode is represented by C [nF] and the total area of the lower ends of the coupling holes is represented by A [?m2], the following expression (1) is satisfied. C/A?1.98 [nF/?m2]??(1) The elution of the second electrode constituting the capacitor at the lower ends of the coupling holes is suppressed.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 31, 2015
    Inventors: Ken OZAWA, Hiroyuki KUNISHIMA
  • Publication number: 20150357335
    Abstract: Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films).
    Type: Application
    Filed: June 3, 2015
    Publication date: December 10, 2015
    Inventors: Hiroyuki Kunishima, Masashige Moritoki, Toshiji Taiji, Youichi Yamamoto
  • Patent number: 8946800
    Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Ippei Kume, Kenichiro Hijioka, Naoya Inoue, Hiroyuki Kunishima, Manabu Iguchi, Hiroki Shirai
  • Publication number: 20130056850
    Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.
    Type: Application
    Filed: August 23, 2012
    Publication date: March 7, 2013
    Inventors: Ippei KUME, Kenichiro Hijioka, Naoya Inoue, Hiroyuki Kunishima, Manabu Iguchi, Hiroki Shirai
  • Patent number: 8357991
    Abstract: A semiconductor device includes an upper interconnect, a lower interconnect, insulating layers interposed between the upper interconnect and the lower interconnect, a connecting portion that is formed in the insulating layers and connects the upper interconnect and the lower interconnect, and an element that is placed in one of the insulating layers and has a conductive layer connected to the connecting portion. The connecting portion is formed over the lower interconnect and the end portions of the conductive layer of the element, and is in contact with the upper face of the lower interconnect and the upper faces and side faces of the end portions of the conductive layer of the element.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: January 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Hiroyuki Kunishima, Norio Okada
  • Patent number: 7981574
    Abstract: Provided is a reticle used for forming a plurality of vias for connecting first wirings provided in a first wiring layer and second wirings provided in a second wiring layer formed above the first wiring layer. The first wirings and the second wirings are provided along one of a first direction and a second direction, and the first direction and the second direction perpendicularly cross each other. The reticle includes a plurality of via opening patterns for forming the plurality of vias. Each of the plurality of via opening patterns has a rectangular shape, and is arranged to cause each side of each of the via opening patterns to be diagonal with respect to the first direction and the second direction.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Kunishima