Patents by Inventor Hiroyuki Kuzuma

Hiroyuki Kuzuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Back annotation apparatus for carrying out a simulation based on the extraction result in regard to parasitic elements
    Patent number: 6965853
    Abstract: A back annotation apparatus, which effectively carries out a back annotation, includes: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verification implementing part for implementing a predetermined layout pattern verification for layout patterns of the logical circuit; a parasitic element extraction part connected to the pre-layout simulation implementing part which extracts parasitic elements from the nodes of which the potential changes; a net list generation part connected to the parasitic element extraction part for generating a net list which includes all the devices included in the layout pattern data and parasitic elements extracted in the parasitic element extraction part; and a post layout simulation implementing part connected to the net list generation part for implementing a post layout simulation by using the net list.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: November 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Kuzuma, Terutoshi Yamasaki
  • Back annotation apparatus for carrying out a simulation based on the extraction result in regard to parasitic elements
    Publication number: 20020013688
    Abstract: A back annotation apparatus, which effectively carries out a back annotation, includes: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verification implementing part for implementing a predetermined layout pattern verification for layout patterns of the logical circuit; a parasitic element extraction part connected to the pre-layout simulation implementing part which extracts parasitic elements from the nodes of which the potential changes; a net list generation part connected to the parasitic element extraction part for generating a net list which includes all the devices included in the layout pattern data and parasitic elements extracted in the parasitic element extraction part; and a post layout simulation implementing part connected to the net list generation part for implementing a post layout simulation by using the net list.
    Type: Application
    Filed: February 2, 2001
    Publication date: January 31, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Kuzuma, Terutoshi Yamasaki