Abstract: An apparatus for processing an image includes a memory for storing the image data of each pixel in the plurality of unit blocks, a direct memory access controller for reading the image data from the memory by accessing the memory on a block-by-block basis by generating the addresses of the pixels in each unit block, and a plurality of image processing modules for receiving the image data of each unit block read based on the addresses generated by the direct memory access controller and sequentially transferred via a data bus, processing the image data of the unit block, and outputting the processed image data of the unit block.

Abstract: A data processing system comprises: a plurality of data processing modules for performing a series of data processing, wherein each of the plurality of data processing modules processes data; a bus connected to each of the plurality of data processing modules; a memory controller for writing the data processed by each of the plurality of data processing modules into a memory via the bus, and for reading out the written data from the memory via the bus; a DMA controller for determining operation of each of the plurality of data processing modules, and outputting an address to the memory controller, the data processed by said data processing module being written at the address and the DMA controller including a data parallel processing control section. The plurality of data processing modules includes first and second data processing modules, and the second data processing module is subsequent to the first data processing module in the series of processing.

Abstract: An apparatus for processing an image comprises a memory for storing the image data of each pixel in the plurality of unit blocks, a direct memory access controller for reading the image data from the memory by accessing the memory on a block-by-block basis by generating the addresses of the pixels in each unit block, and a plurality of image processing modules for receiving the image data of each unit block read based on the addresses generated by the direct memory access controller and sequentially transferred via a data bus, processing the image data of the unit block, and outputting the processed image data of the unit block.

Abstract: A data processing system comprises: a plurality of data processing modules for performing a series of data processing, wherein each of the plurality of data processing modules processes data; a bus connected to each of the plurality of data processing modules; a memory controller for writing the data processed by each of the plurality of data processing modules into a memory via the bus, and for reading out the written data from the memory via the bus; a DMA controller for determining operation of each of the plurality of data processing modules, and outputting an address to the memory controller, the data processed by said data processing module being written at the address and the DMA controller including a data parallel processing control section. The plurality of data processing modules includes first and second data processing modules, and the second data processing module is subsequent to the first data processing module in the series of processing.