Abstract: Provided is a fat simulating composition containing an aqueous phase and an oil phase dispersed in the aqueous phase, in which a melting point or a crystallization temperature of the oil phase is in a range of from ?20° C. to 60° C., and an absolute value of a difference between a d-line refractive index of the aqueous phase and a d-line refractive index of the oil phase satisfies a relationship of 0.01?|oil phase refractive index?aqueous phase refractive index|?0.115.

Abstract: A negative electrode including: a negative electrode current collector with a roughened surface; and a negative electrode active material layer provided on the negative electrode current collector. The negative electrode active material layer includes: negative electrode active material particles containing a compound of lithium, silicon, and oxygen; and a composite compound filled in interparticle gaps and a surface layer of the negative electrode active material particles, the composite compound at least containing chemically bonded carbon and oxygen atoms, the composite compound not being alloyed with the negative electrode active material particles. A ratio O/Si of the oxygen to the silicon constituting the negative electrode active material particles is in the range of 0.8 or more and 1.2 or less.

Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFB) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFB provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFB) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFB provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

Abstract: Provided is a joint component manufacturing method for reducing occurrence of burrs upon bonding between a first member having a hole and a second member having a shaft portion and firmly bonding both members. In the method for manufacturing a joint component 100, a hole-side weak press-fit portion 112 is formed at a hole 111 of a flat plate ring-shaped first member 110. Moreover, each of a shaft-side weak press-fit portion 122 and a shaft-side strong press-fit portion 124 is formed at a shaft portion 121 of a cylindrical second member 120. The hole-side weak press-fit portion 112 and the shaft-side weak press-fit portion 122 are defined by a first weak press-fit interference Lw1 formed thinner than a first strong press-fit interference Ls1. The shaft-side strong press-fit portion 124 is defined by a first strong press-fit interference Ls1 as the minimum necessary press-fit interference for electric resistance welding upon electric resistance welding between the hole 111 and the shaft portion 121.

Abstract: Provided is a joint component manufacturing method for reducing occurrence of burrs upon bonding between a first member having a hole and a second member having a shaft portion and firmly bonding both members. In the method for manufacturing a joint component 100, a hole-side weak press-fit portion 112 is formed at a hole 111 of a flat plate ring-shaped first member 110. Moreover, each of a shaft-side weak press-fit portion 122 and a shaft-side strong press-fit portion 124 is formed at a shaft portion 121 of a cylindrical second member 120. The hole-side weak press-fit portion 112 and the shaft-side weak press-fit portion 122 are defined by a first weak press-fit interference Lw1 formed thinner than a first strong press-fit interference Ls1. The shaft-side strong press-fit portion 124 is defined by a first strong press-fit interference Ls1 as the minimum necessary press-fit interference for electric resistance welding upon electric resistance welding between the hole 111 and the shaft portion 121.

Abstract: Provided is a joint component manufacturing method for reducing occurrence of burrs upon bonding between a first member having a hole and a second member having a shaft portion and firmly bonding both members. In the method for manufacturing a joint component 100, a hole-side weak press-fit portion 112 is formed at a hole 111 of a flat plate ring-shaped first member 110. Moreover, each of a shaft-side weak press-fit portion 122 and a shaft-side strong press-fit portion 124 is formed at a shaft portion 121 of a cylindrical second member 120. The hole-side weak press-fit portion 112 and the shaft-side weak press-fit portion 122 are defined by a first weak press-fit interference Lw1 formed thinner than a first strong press-fit interference Ls1. The shaft-side strong press-fit portion 124 is defined by a first strong press-fit interference Ls1 as the minimum necessary press-fit interference for electric resistance welding upon electric resistance welding between the hole 111 and the shaft portion 121.

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

Abstract: Provided is a joint component manufacturing method for reducing occurrence of burrs upon bonding between a first member having a hole and a second member having a shaft portion and firmly bonding both members. In the method for manufacturing a joint component 100, a hole-side weak press-fit portion 112 is formed at a hole 111 of a flat plate ring-shaped first member 110. Moreover, each of a shaft-side weak press-fit portion 122 and a shaft-side strong press-fit portion 124 is formed at a shaft portion 121 of a cylindrical second member 120. The hole-side weak press-fit portion 112 and the shaft-side weak press-fit portion 122 are defined by a first weak press-fit interference Lw1 formed thinner than a first strong press-fit interference Ls1. The shaft-side strong press-fit portion 124 is defined by a first strong press-fit interference Ls1 as the minimum necessary press-fit interference for electric resistance welding upon electric resistance welding between the hole 111 and the shaft portion 121.

Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.

Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles: validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

Abstract: An image projection apparatus (1) is an image projection apparatus in which an optical axis of a projection lens (19) for projecting an image and a center position of an image formation area on a light modulation element (32) may be displaced relative to each other, and the image projection apparatus includes electronic zoom means (13) for magnifying or reducing a size of the image formation area on the light modulation element by electronic zooming centered at a predetermined position, and control means (14) for controlling the electronic zoom unit to perform the electronic zooming with the predetermined position as the optical axis.

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

Abstract: When a retake button is selected, a CPU causes a dialog screen for inputting a reason for a photographic error to be displayed. On the dialog screen, the name of a radiographer who is logging onto an X-ray photographing apparatus and select buttons indicating possible reasons for photographic errors are indicated. The CPU transmits an unsatisfactorily photographed image to a different server.

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

Abstract: When a retake button is selected, a CPU causes a dialog screen for inputting a reason for a photographic error to be displayed. On the dialog screen, the name of a radiographer who is logging onto an X-ray photographing apparatus and select buttons indicating possible reasons for photographic errors are indicated. The CPU transmits an unsatisfactorily photographed image to a different server.