Abstract: A bipolar transistor in which a buried collector region, a base region and an emitter region are formed in a device forming region surrounded by an isolation region and in which a base contact electrode and a collector contact electrode are arranged in symmetry with each other, and a process for preparing the transistor. The collector contact electrode is formed through an opening formed in a portion of the isolation region for connection with the buried collector region. In this manner, the collision between the base region and the collector contact region may be avoided effectively.

Abstract: A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.

Abstract: In a semiconductor device having trench-shaped element isolating regions formed in a semiconductor body and also a conductive layer extending on each element isolating region and connected to an impurity diffusion region of the semiconductor body, there is formed an insulator layer region between an extension of the conductive layer and the element isolating region, and the insulator layer region is buried in the surface portion of the semiconductor body. In such construction, the insulation space between the conductive layer and the semiconductor body can be increased while the distance between the element isolating region and the impurity diffusion region can be shortened to consequently diminish the parasitic capacitance between the conductive layer and the semiconductor body, hence attaining a faster operation in the semiconductor device.