Patents by Inventor Hiroyuki Miyakawa

Hiroyuki Miyakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6365957
    Abstract: An object of the present invention is to provide a lateral bipolar transistor having a high current driving capacity and a high current amplification factor as well as a high cut-off frequency. A device area 13 surrounded by an isolating insulation layer is formed on the surface of a semiconductor substrate 11. A base area 15 is formed in the device area 13 to a specified depth from the surface of the semiconductor substrate 11. A core insulation layer 25 is formed in the base area 15 with a depth shallower than the base area 15 from the surface of the semiconductor substrate 11. Around the core insulation layer 25, there are formed emitter areas 26. A collector area 17 is formed at a specified distance from the emitter area 26. Since the bottom area of the emitter area 26 is reduced by being provided with the core insulation layer 25 without reducing the side area of the emitter area 26, the current driving capacity and the current amplification factor of the transistor are thus improved.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: April 2, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Miyakawa
  • Patent number: 5675173
    Abstract: The opening width of an element isolating trench is Wa'. The opening width of a substrate potential setting trench is Wb'. When the maximum film thickness of a polysilicon film lying on the side wall of each of the trenches is set to t, the opening width Wa' of the element isolating trench and the opening width Wb' of the substrate potential setting trench satisfies a condition that (Wa'-2t)<(Wb'-2t) and Wa'>2t. A silicon oxide film covers the entire portion of the internal surface of the element isolating trench and covers the internal surface of the substrate potential setting trench except the bottom portion thereof. Therefore, the polysilicon film in the element isolating trench is set in the electrically floating state and the polysilicon film in the substrate potential setting trench is connected to the semiconductor substrate.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: October 7, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Kawai, Hiroyuki Miyakawa, Koji Kimura