Patents by Inventor Hiroyuki Miyake

Hiroyuki Miyake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967598
    Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Umezaki, Hiroyuki Miyake
  • Patent number: 11961842
    Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Publication number: 20240113130
    Abstract: A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Shunpei YAMAZAKI, Hiroyuki MIYAKE, Hideaki SHISHIDO, Jun KOYAMA
  • Publication number: 20240105737
    Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Hisao IKEDA, Kouhei TOYOTAKA, Hideaki SHISHIDO, Hiroyuki MIYAKE, Kohei YOKOYAMA, Yasuhiro JINBO, Yoshitaka DOZEN, Takaaki NAGATA, Shinichi HIRASA
  • Patent number: 11942170
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Patent number: 11942058
    Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Hiroyuki Miyake
  • Publication number: 20240094775
    Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yoshiharu HIRAKATA, Hiroyuki MIYAKE, Seiko INOUE, Shunpei YAMAZAKI
  • Patent number: 11916088
    Abstract: First to fourth switches are provided so that conduction states are able to be controlled independently of each other. The first switch, the third switch, and the second switch are electrically connected in series between a first wiring and a third wiring. The fourth switch has a function of controlling a conduction state between the light-emitting element and a fourth wiring. In a first transistor, a gate is electrically connected to a node to which the third switch and the second switch are electrically connected, one of a source and a drain is electrically connected to a second wiring, and the other is electrically connected to the light-emitting element. A capacitor includes first and second electrodes, the first electrode is electrically connected to a node to which the first switch and the third switch are electrically connected, and the second electrode is electrically connected to the light-emitting element.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 27, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Miyake
  • Publication number: 20240061292
    Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 22, 2024
    Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
  • Publication number: 20240049555
    Abstract: A flexible touch panel is provided. Both reduction in thickness and high sensitivity of a touch panel are achieved. The touch panel includes a first flexible substrate, a first insulating layer over the first substrate, a transistor and a light-emitting element over the first insulating layer, a color filter over the light-emitting element, a pair of sensor electrodes over the color filter, a second insulating layer over the sensor electrodes, a second flexible substrate over the second insulating layer, and a protective layer over the second substrate. A first bonding layer is between the light-emitting element and the color filter. The thickness of the first substrate and the second substrate is each 1 ?m to 200 ?m inclusive. The first bonding layer includes a region with a thickness of 50 nm to 10 ?m inclusive.
    Type: Application
    Filed: October 4, 2023
    Publication date: February 8, 2024
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA, Hiroyuki MIYAKE
  • Patent number: 11881489
    Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: January 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Kouhei Toyotaka, Hideaki Shishido, Hiroyuki Miyake, Kohei Yokoyama, Yasuhiro Jinbo, Yoshitaka Dozen, Takaaki Nagata, Shinichi Hirasa
  • Patent number: 11869453
    Abstract: To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n?3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 9, 2024
    Inventors: Hiroyuki Miyake, Kouhei Toyotaka, Shunpei Yamazaki
  • Publication number: 20230395172
    Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 7, 2023
    Inventors: Masayuki SAKAKURA, Yuugo GOTO, Hiroyuki MIYAKE, Daisuke KUROSAKI
  • Publication number: 20230393688
    Abstract: A touch panel with higher sensing accuracy or higher detection sensitivity is provided. The touch panel includes a first conductive layer, a second conductive layer, a plurality of display elements, and a scan line. In a plan view, the first conductive layer has an outline including a first portion that is linear and parallel to a first direction. In the plan view, the second conductive layer has an outline including a second portion that is linear and parallel to the first direction. The first portion and the second portion face each other. The display element is in a position not overlapping with the first conductive layer nor the second conductive layer. The scan line has a portion extending in a second direction. An angle between the first direction and the second direction is greater than or equal to 300 and less than or equal to 60°.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hiroyuki MIYAKE
  • Publication number: 20230395028
    Abstract: A light-emitting device in which variation in luminance of pixels is suppressed. A light-emitting device includes at least a transistor, a first wiring, a second wiring, a first switch, a second switch, a third switch, a fourth switch, a capacitor, and a light-emitting element. The first wiring and a first electrode of the capacitor are electrically connected to each other through the first switch. A second electrode of the capacitor is connected to a first terminal of the transistor. The second wiring and a gate of the transistor are electrically connected to each other through the second switch. The first electrode of the capacitor and the gate of the transistor are electrically connected to each other through the third switch. The first terminal of the transistor and an anode of the light-emitting element are electrically connected to each other through the fourth switch.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: Seiko INOUE, Hiroyuki MIYAKE
  • Patent number: 11836007
    Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: December 5, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Hiroyuki Miyake, Seiko Inoue, Shunpei Yamazaki
  • Patent number: 11837461
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 5, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
  • Patent number: 11828613
    Abstract: Provided is a superimposed-image display device configured such that when there is a guidance divergence point, which is a guidance target, ahead in a traveling direction of a vehicle, a plurality of guidance objects that provide guidance on an entry route that enters the guidance divergence point and an exit route are displayed. When a course including the entry route, the guidance divergence point, and the exit route is displayed using a plurality of guidance objects, the plurality of guidance objects are displayed so as to match the elevation of the line of sight of an occupant and displayed so as to be shifted to locations that are on the opposite side to an exit direction at the guidance divergence point relative to the front of the vehicle.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: November 28, 2023
    Assignee: AISIN CORPORATION
    Inventors: Hiroyuki Miyake, Kenji Watanabe, Takashi Kawai
  • Publication number: 20230376076
    Abstract: To increase the detection sensitivity of a touch panel, provide a thin touch panel, provide a foldable touch panel, or provide a lightweight touch panel. A display element and a capacitor forming a touch sensor are provided between a pair of substrates. Preferably, a pair of conductive layers forming the capacitor each have an opening. The opening and the display element are provided to overlap each other. A light-blocking layer is provided between a substrate on the display surface side and the pair of conductive layers forming the capacitor.
    Type: Application
    Filed: April 19, 2023
    Publication date: November 23, 2023
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Koji KUSUNOKI, Hiroyuki MIYAKE, Kazunori WATANABE
  • Publication number: 20230378188
    Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.
    Type: Application
    Filed: April 17, 2023
    Publication date: November 23, 2023
    Inventor: Hiroyuki MIYAKE