Patents by Inventor Hiroyuki Miyake
Hiroyuki Miyake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250142973Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.Type: ApplicationFiled: January 6, 2025Publication date: May 1, 2025Inventors: Kouhei TOYOTAKA, Jun KOYAMA, Hiroyuki MIYAKE
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Publication number: 20250140216Abstract: A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.Type: ApplicationFiled: November 8, 2024Publication date: May 1, 2025Inventor: Hiroyuki MIYAKE
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Publication number: 20250120181Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Inventors: Yutaka SHIONOIRI, Hiroyuki MIYAKE, Kiyoshi KATO
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Patent number: 12271233Abstract: To increase the detection sensitivity of a touch panel, provide a thin touch panel, provide a foldable touch panel, or provide a lightweight touch panel. A display element and a capacitor forming a touch sensor are provided between a pair of substrates. Preferably, a pair of conductive layers forming the capacitor each have an opening. The opening and the display element are provided to overlap each other. A light-blocking layer is provided between a substrate on the display surface side and the pair of conductive layers forming the capacitor.Type: GrantFiled: April 19, 2023Date of Patent: April 8, 2025Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Kusunoki, Hiroyuki Miyake, Kazunori Watanabe
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Publication number: 20250098315Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.Type: ApplicationFiled: September 26, 2024Publication date: March 20, 2025Inventor: Hiroyuki MIYAKE
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Publication number: 20250076712Abstract: A display device with less light leakage and excellent contrast is provided. A display device having a high aperture ratio and including a large-capacitance capacitor is provided. A display device in which wiring delay due to parasitic capacitance is reduced is provided. A display device includes a transistor over a substrate, a pixel electrode connected to the transistor, a signal line electrically connected to the transistor, a scan line electrically connected to the transistor and intersecting with the signal line, and a common electrode overlapping with the pixel electrode and the signal line with an insulating film provided therebetween. The common electrode includes stripe regions extending in a direction intersecting with the signal line.Type: ApplicationFiled: November 4, 2024Publication date: March 6, 2025Inventors: Ryo HATSUMI, Daisuke KUBOTA, Hiroyuki MIYAKE
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Publication number: 20250076720Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.Type: ApplicationFiled: March 8, 2024Publication date: March 6, 2025Inventors: Atsushi Umezaki, Hiroyuki Miyake
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Publication number: 20250076932Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.Type: ApplicationFiled: October 3, 2024Publication date: March 6, 2025Inventors: Yoshiharu HIRAKATA, Hiroyuki MIYAKE, Seiko INOUE, Shunpei YAMAZAKI
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Publication number: 20250072115Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Inventors: Hisao IKEDA, Kouhei TOYOTAKA, Hideaki SHISHIDO, Hiroyuki MIYAKE, Kohei YOKOYAMA, Yasuhiro JINBO, Yoshitaka DOZEN, Takaaki NAGATA, Shinichi HIRASA
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Publication number: 20250046799Abstract: A power storage device having high capacitance is provided. A power storage device with excellent cycle characteristics is provided. A power storage device with high charge and discharge efficiency is provided. A power storage device including a negative electrode with low resistance is provided. A negative electrode for a power storage device includes a number of composites in particulate forms. The composites include a negative electrode active material, a first functional material, and a compound. The compound includes a constituent element of the negative electrode active material and a constituent element of the first functional material. The negative electrode active material includes a region in contact with at least one of the first functional material or the compound.Type: ApplicationFiled: September 6, 2024Publication date: February 6, 2025Inventors: Hiroyuki MIYAKE, Nobuhiro INOUE, Ryo YAMAUCHI, Mako MOTOYOSHI, Takahiro KAWAKAMI, Mayumi MIKAMI, Miku FUJITA, Shunpei YAMAZAKI
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Publication number: 20250020960Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: ApplicationFiled: September 26, 2024Publication date: January 16, 2025Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
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Patent number: 12199106Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.Type: GrantFiled: May 16, 2023Date of Patent: January 14, 2025Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kouhei Toyotaka, Jun Koyama, Hiroyuki Miyake
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Publication number: 20250014532Abstract: The liquid crystal display device includes a first substrate provided with a terminal portion, a switching transistor, a driver circuit portion, and a pixel circuit portion including a pixel transistor and a plurality of pixels, a second substrate provided with a common electrode electrically connected to the terminal portion through the switching transistor, and liquid crystal between a pixel electrode and the common electrode. In a period during which a still image is switched to a moving image, the following steps are sequentially performed: a first step of supplying the common potential to the common electrode; a second step of supplying a power supply voltage to the driver circuit portion; a third step of supplying a clock signal to the driver circuit portion; and a fourth step of supplying a start pulse signal to the driver circuit portion.Type: ApplicationFiled: July 18, 2024Publication date: January 9, 2025Inventors: Jun KOYAMA, Hiroyuki MIYAKE
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Patent number: 12193244Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.Type: GrantFiled: August 19, 2022Date of Patent: January 7, 2025Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Shionoiri, Hiroyuki Miyake, Kiyoshi Kato
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Publication number: 20240421161Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.Type: ApplicationFiled: August 28, 2024Publication date: December 19, 2024Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE
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Patent number: 12170291Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.Type: GrantFiled: December 11, 2023Date of Patent: December 17, 2024Inventors: Hisao Ikeda, Kouhei Toyotaka, Hideaki Shishido, Hiroyuki Miyake, Kohei Yokoyama, Yasuhiro Jinbo, Yoshitaka Dozen, Takaaki Nagata, Shinichi Hirasa
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Patent number: 12151560Abstract: A superimposed image display device is configured to: acquire a recommended lane in which a vehicle is recommended to travel on a road on which the vehicle is currently traveling; identify a lane of travel that is a lane in which the vehicle is currently traveling on the road on which the vehicle is currently traveling; acquire a confidence indicating how confident an identification result of the lane of travel is; and display a guide object providing guidance on the recommended lane in a display mode according to the confidence.Type: GrantFiled: October 28, 2022Date of Patent: November 26, 2024Assignee: AISIN CORPORATIONInventors: Hiroyuki Miyake, Daisuke Kobayashi
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Publication number: 20240377682Abstract: A display device with less light leakage and excellent contrast is provided. A display device having a high aperture ratio and including a large-capacitance capacitor is provided. A display device in which wiring delay due to parasitic capacitance is reduced is provided. A display device includes a transistor over a substrate, a pixel electrode connected to the transistor, a signal line electrically connected to the transistor, a scan line electrically connected to the transistor and intersecting with the signal line, and a common electrode overlapping with the pixel electrode and the signal line with an insulating film provided therebetween. The common electrode includes stripe regions extending in a direction intersecting with the signal line.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Ryo HATSUMI, Daisuke KUBOTA, Hiroyuki MIYAKE
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Patent number: 12142238Abstract: A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.Type: GrantFiled: April 20, 2023Date of Patent: November 12, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hiroyuki Miyake
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Publication number: 20240363181Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Inventors: Masayuki SAKAKURA, Yuugo GOTO, Hiroyuki MIYAKE, Daisuke KUROSAKI