Abstract: A novel silver-coated copper powder, particularly a silver-coated copper powder particle having a dendritic shape, having increased electrical conductivity with no need to increase the silver content is provided. The silver-coated copper powder is composed of a silver-coated copper particle coated with a silver layer containing silver or a silver alloy, including a silver-coated copper particle having a dendritic shape, containing nitrogen (N) in the silver layer, and having a nitrogen (N) content of 0.2 to 10.0 parts by mass with respect to 100 parts by mass of the silver content.

Abstract: A new dendritic silver powder can be mixed with a synthetic resin to give electroconductive films having sufficient electroconductivity. Even when the films vary in thickness, the electroconductivity of the films can be maintained. The volume-cumulative particle diameter D50 (referred to as “D50D”) determined by adding the silver powder to water containing a dispersant, applying 300-watt ultrasonic waves to the resultant mixture for 3 minutes, and examining the dispersion with a laser diffraction/scattering type particle size analyzer is 1.0-15.0 ?m and that the ratio of the volume-cumulative particle diameter D50 (referred to as “D50N”) determined by adding the silver powder to the water containing a dispersant and examining the mixture under the same conditions as for the D50D except that no ultrasonic waves are applied, to the D50D, D50N/D50D, is 1.0-10.0.

Abstract: A novel silver-coated copper powder, particularly a silver-coated copper powder particle having a dendritic shape, having increased electrical conductivity with no need to increase the silver content is provided. The silver-coated copper powder is composed of a silver-coated copper particle coated with a silver layer containing silver or a silver alloy, including a silver-coated copper particle having a dendritic shape, containing nitrogen (N) in the silver layer, and having a nitrogen (N) content of 0.2 to 10.0 parts by mass with respect to 100 parts by mass of the silver content.

Abstract: Disclosed is a new dendritic silver powder which, when mixed with a synthetic resin, gives electroconductive films having sufficient electroconductivity. Even when the films produced from a mixture of the dendritic silver powder and a synthetic resin vary in thickness, the electroconductivity of the films can be maintained. The volume-cumulative particle diameter D50 (referred to as “D50D”) determined by adding the silver powder to water containing a dispersant, applying 300-watt ultrasonic waves to the resultant mixture for 3 minutes, and examining the dispersion with a laser diffraction/scattering type particle size analyzer is 1.0-15.0 ?m and that the ratio of the volume-cumulative particle diameter D50 (referred to as “D50”) determined by adding the silver powder to the water containing a dispersant and examining the mixture under the same conditions as for the D50D except that no ultrasonic waves are applied, to the D50D, D50N/D50D, is 1.0-10.0.

Abstract: An instruction analyzing unit sequentially analyzes instructions of a program which is inputted to a program inputting unit. A NOP instruction analyzing part encodes continuous NOP instructions as one continuous NOP instruction. An instruction code outputting unit outputs the instruction encoded by the instruction analyzing unit as an object code. Therefore, the size of the object code can be reduced.

Abstract: A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i−1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.

Abstract: A method of manufacturing a reversible heat-sensitive recording medium capable of manufacturing a reversible heat-sensitive recording medium invulnerable toward scratches, etc. even when printing/erasing is repeated under situation where dirt and dust tend to attach to the reversible heat-sensitive recording medium, thus providing increase durability of the reversible heat-sensitive recording medium against repeated printing/erasing. In the method of manufacturing the reversible heat-sensitive recording medium containing a reversible heat-sensitive recording layer and a substrate sheet, a reversible heat-sensitive recording sheet or a reversible heat-sensitive recording transfer sheet having the reversible heat-sensitive recording layer applied to the substrate sheet through welding, after which a protective layer is formed on the reversible heat-sensitive recording layer.

Abstract: A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i-1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.

Abstract: A semiconductor integrated circuit and a method for reducing the consumed power are provided. A comparator outputs bits having the same level, which correspond to each other, of a last input stored in a register and a current input that acts as an input signal. A zero counter counts the number of the bits having the same level output from the comparator. If the number of the bits having the same level is smaller than a predetermined number, the current input is not similar to the last input. Consequently, an instruction is given to a flip-flop to invert the current input. The inverted current input becomes similar to the last input. Thus, the consumed power of a logic can be reduced.

Abstract: A reversible heat-sensitive recording medium has a substrate where a reversible heat-sensitive recording layer and a protective layer are successively formed on top of it. The reversible heat-sensitive recording layer is formed by a reversible heat-sensitive recording material including a leuco dye and a color developing/reducing agent. The color developing/reducing agent is a combination of two kinds of color developing/reducing agents, one with a high color developing ability and the other with high image preservation and stabilization capabilities. The two agents are combined at a ratio between 1:4 to 4:1. Thus a reversible heat-sensitive recording material with a fine color developing ability and high image preservation and stabilization capabilities can be obtained.

Abstract: In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers.

Abstract: A highly reliable data holding circuit with a reduced circuit area and reduced power consumption is disclosed. Output terminals (DO, DOB) are connected to input terminals (DI, DIB) receiving signals at H and L levels (potentials VDD and GND) in mutually exclusive relation through transistors (MN2, MN1) and inverters (INV1, INV2). Input terminals of the inverters (INV1, INV2) are connected to power supplies (VDD) through transistors (MP2, MP1) having gate electrodes connected to output terminals of the inverters (INV2, INV1), respectively. The transistors (MN2, MN1) cause a voltage drop of the signals to be applied to the inverters (INV1, INV2) by the amount of a threshold voltage (Vthn). One of the transistors (MP1, MP2) which receives a signal at L level at its control terminal provides a potential (VDD) to the input terminal of one of the inverters (INV1, INV2) which is to output a signal at L level, compensating for the voltage drop by the amount of the threshold voltage (Vthn).

Abstract: A logic circuit (L.sub.i) is connected between a virtual power supply line (VDDV) connected to an actual power supply (VDD) through a PMOS transistor (Q1) and a virtual grounding line (GNDV) connected to an actual ground (GND) through an NMOS transistor (Q2). During an active period, the transistors (Q1, Q2) are constantly conducting, and the virtual power supply line (VDDV) and virtual grounding line (GNDV) are at the power supply potential (VDD) and ground potential (GND), respectively. During a standby period, the transistors (Q1, Q2) periodically repeat conduction/non-conduction to charge and discharge the virtual power supply line (VDDV) and virtual grounding line (GNDV), suppressing power consumption while preventing loss of information held by the logic circuit (L.sub.i).

Abstract: A semiconductor integrated circuit device having a SOI structure which can prevent a deterioration in the breakdown voltage of a transistor without damaging integration, and a method for manufacturing the semiconductor integrated circuit device are obtained. An embedded oxide film is not formed over the whole face of a P type silicon layer but has an opening in a region which is placed below a gate electrode. The opening is filled in to form a penetration P layer. Accordingly, a SOI layer is electrically connected to the P type silicon layer through the penetration P layer. The plane position and shape of the gate electrode conform to those of the penetration P layer.

Abstract: To obtain a semiconductor integrated circuit reduced in hardware size, by avoiding duplication of a common constitution. A logic block (100) comprises logic means (A), logic means (B), and logic means (C), and the output of a pipeline register (11) is connected to the logic means (A) through a signal line (a), and the logic means (A) and logic means (B) are connected through a signal line (b). The logic means (A) is also connected to the logic means (C) through a signal line (c), and the logic means (C) is connected to the input of a pipeline register (21) through a signal line (d). When performing the same logic action in the first half period and second half period of a clock signal, it is not necessary to install two identical logic means, so that the size of the hardware may be reduced as compared with the constitution of installing two identical logic means.

Abstract: In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers.

Abstract: An adder including a first exclusive OR device, a second exclusive OR device for receiving an output of the first exclusive OR device and a generating signal G(i-1), exclusive ORing the output result of the first exclusive OR device and the generating signal G(i-1), and outputting the calculated result as a sum Si0, and a third exclusive OR device for receiving an output of the second exclusive OR device and a propagating signal P(i-1), exclusive ORing the output result of the second exclusive OR device and the propagating signal P(i-1), and outputting the calculated result as a sum Si1, whereby the amount of hardware and power consumption of the adder used in a carry selecting system is reduced.