Patents by Inventor Hiroyuki Motizuki

Hiroyuki Motizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for quantitative quality inspection of substrate such as wafer
    Patent number: 7012680
    Abstract: A method for a quantitative evaluation of a substrate such as wafer defines a number of sequential first regions so that each of the first regions overlaps the adjacent region. A surface data (e.g., thickness data) in each of the first regions is used to determine a normal vector representing a surface configuration (e.g., thickness variation) of the first region. Then, an angular difference between the normal vectors is determined for each combination of adjacent two first regions. Subsequently, the determined angular difference is compared with a reference to evaluate a quality of a second region including at least one of the first regions, e.g., chip region, strip-like region and/or the entire of the wafer.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: March 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keishi Kubo, Masateru Doi, Hiroyuki Motizuki, Keiichi Yoshizumi
  • Method and apparatus for quantitative quality inspection of substrate such as wafer
    Publication number: 20040090639
    Abstract: A method for a quantitative evaluation of a substrate such as wafer defines a number of sequential first regions so that each of the first regions overlaps the adjacent region. A surface data (e.g., thickness data) in each of the first regions is used to determine a normal vector representing a surface configuration (e.g., thickness variation) of the first region. Then, an angular difference between the normal vectors is determined for each combination of adjacent two first regions. Subsequently, the determined angular difference is compared with a reference to evaluate a quality of a second region including at least one of the first regions, e.g., chip region, strip-like region and/or the entire of the wafer.
    Type: Application
    Filed: July 15, 2003
    Publication date: May 13, 2004
    Inventors: Keishi Kubo, Masateru Doi, Hiroyuki Motizuki, Keiichi Yoshizumi